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Survival guide to high-speed ADC digital outputs

Posted: 18 Apr 2012 ?? ?Print Version ?Bookmark and Share

Keywords:analog-to-digital converters? digital data outputs? CMOS? LVDS? CML?

With the plethora of analog-to-digital converters (ADCs) available for designers to choose from, an important parameter to consider in the selection process is the type of digital data outputs included. Currently, the three most common types of digital outputs utilized by high speed converters are complementary metal oxide semiconductor (CMOS), low-voltage differential signaling (LVDS), and current-mode logic (CML).

Each of the digital-output types used in ADCs has advantages and disadvantages that designers should consider in their particular application. These factors depend on the sampling rate and resolution of the ADC, the output data rates, the power requirements of the system design, and others.

In this article, the electrical specifications of each type of output will be discussed, along with what makes each type suited for its particular application. These different types of outputs will be compared in terms of physical implementation, efficiency, and the applications best suited for each type.

CMOS digital output drivers
In ADCs with sample rates of less than 200 megasamples/sec (Msps), it is common to find that the digital outputs are CMOS. A typical CMOS driver consists of two transistorsone NMOS and one PMOSconnected between the power supply (VDD) and ground as shown in figure 1a. This structure results in an inversion in the output, so as an alternative, the back-to-back structure in figure 1b can be used, to avoid the inversion in the output.

The input of the CMOS output driver is high impedance while the output is low impedance. At the input to the driver, the impedance of the gates of the two CMOS transistors is quite high, since the gate is isolated from any conducting material by the gate oxide. The impedances at the input can range from k? to M?.

At the output of the driver, the impedance is governed by the drain current, ID, which is typically small. In this case, the impedance is usually less than a few hundred ohms. The voltage levels for CMOS swing from approximately VDD to ground and can therefore be quite large depending on the magnitude of VDD.

Figure 1: Typical CMOS digital output driver: (left) inverted output; (right) non-inverted output.

Since the input impedance is high and the output impedance is relatively low, an advantage that CMOS has is that one output can typically drive multiple CMOS inputs.

Another advantage to CMOS is the low static current. The only instance where there is significant current flow is during a switching event on the CMOS driver. When the driver is in either a low state (pulled to ground), or in a high state (pulled to VDD), there is little current flow through the driver. However, when the driver is switching from a low state to a high state or from a high state to a low state, there is momentarily a low-resistance path from VDD to ground. This transient current is one of the main reasons why other technologies are used for output drivers when converter speeds go beyond 200 MSPS.

Another reason is that a CMOS driver is required for each bit of the converter. If a converter has 14 bits, there are 14 CMOS output drivers required to transmit each of those bits. Commonly, more than one converter is placed in a given package and up to eight converters in a single package are common.

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