Survival guide to high-speed ADC digital outputs(2)

When using CMOS technology, this could mean that there would be up to 112 output pins required just for the data outputs. Not only would this be prohibitive from a packaging standpoint, but it would also have high power consumption and increase the complexity of board layout. To combat these issues, an interface using LVDS was introduced.

LVDS digital output drivers
LVDS offers some nice advantages over CMOS technology. It operates with a low-voltage signal, approximately 350 mV, and is differential rather than single-ended. The lower voltage swing has a faster switching time and reduces EMI concerns.

By virtue of being differential, there is also the benefit of common-mode rejection. This means that noise coupled to the signals tends to be common to both signal paths and is mostly canceled out by the differential receiver.

The impedances in LVDS need to be more tightly controlled. In LVDS, the load resistance needs to be approximately 100 ? and is usually achieved by a parallel termination resistor at the LVDS receiver. In addition, the LVDS signals need to be routed using controlled-impedance transmission lines. The singled-ended impedance required is 50 ? while the differential impedance is maintained at 100 ?. Figure 2 shows the typical LVDS output driver.

Figure 2: Typical LVDS output driver.

As shown by the topology of the LVDS output driver in figure 2, the circuit operation results in a fixed DC-load current on the output supplies. This avoids current spikes that would be seen in a typical CMOS output driver when the output logic state transitions. The nominal current source/sink in the circuit is set to 3.5 mA, which results in a typical output voltage swing of 350 mV with a 100 ? termination resistor. The common mode level of the circuit is typically set to 1.2 V, which is compatible with 3.3 V, 2.5V, and 1.8 V supply voltages.

There are two standards that have been written to define the LVDS interface. The most commonly used the ANSI/TIA/EIA-644 specification entitled "Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits." The other is the IEEE standard 1596.3 entitled "IEEE Standard for Low Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI)."

LVDS does require that more careful attention be paid to the physical layout of the routing of the signals, but offers many advantages for converters when sampling at speeds of 200 MSPS or greater. The constant current of the LVDS driver allows for many outputs to be driven without the large amount of current draw that CMOS would require.

In addition, it is possible to operate LVDS in a double-data rate (DDR) mode, where two data bits can be routed through the same LVDS output driver. This reduces the number of pins required by one half, compared to CMOS.

Also, the amount of power consumed for the same number of data outputs is reduced. LVDS does offer numerous benefits over CMOS for the data outputs of converters, but it eventually has its limitations as CMOS does. As converter resolution increases, the number of data outputs required by an LVDS interface becomes more difficult to manage for PCB layouts. Furthermore, the sample rates of converters eventually push the required data rates of the interface beyond the capabilities of LVDS.

CML output drivers
The latest trend in digital output interfaces for converters is to use a serialized interface that uses current mode logic (CML) output drivers. Typically converters with higher resolutions (≥14 bits), higher speeds (≥200 Msps), and the desire for smaller packages with reduced power use these types of drivers. The CML output driver is employed in JESD204 interfaces that are being used on the latest converters.

Utilizing CML drivers with serialized JESD204 interfaces allows data rates on the converters outputs to go up to 12Gbit/s (with the current revision of the specification JESD204B). In addition, the number of output pins required is dramatically reduced. Routing a separate clock signal is no longer necessary since the clock becomes embedded in the 8b/10b encoded data stream.