Survival guide to high-speed ADC digital outputs(4)

In addition, there is a clock signal that needs to be routed and aligned with the data outputs. Careful attention must be given to the routing paths between the clock output and the data outputs also to ensure that the skew is not too large.

In the case of CML in the JESD204 interface, attention must also be paid to the routing paths between the digital outputs. There are significantly fewer data outputs to manage, so this task does become easier, but it cannot be neglected altogether. There is no worry in this case with regards to timing skew between the data outputs and the clock output, since the clock is embedded in the data. However, attention must be given to an adequate clock and data recovery (CDR) circuit in the receiver.

In addition to the skew, the setup and hold times with CMOS and LVDS must also be watched carefully. The data outputs must be driven to their appropriate logic state in sufficient time before the edge transition of the clock, and must be maintained in that logic state for a sufficient time after the edge transition of the clock. This can be affected by the skew between the data outputs and the clock outputs, so it is important to maintain good timing relationships.

LVDS has the advantage over CMOS due to the lower signal swings and differential signaling. The LVDS output driver does not have to drive such a large signal to many different outputs and does not draw a large amount of current from the power supply when switching logic states as the CMOS driver would. This makes it less likely for there to be an issue delivering a change in logic state.

If there were many CMOS drivers switching simultaneously, the power-supply voltage could get pulled down and introduce issues driving the right logic values to the receiver. The LVDS drivers would maintain a constant level of current such that this particular issue would not arise. In addition, the LVDS drivers are inherently more immune to common-mode noise due to its use of differential signaling.

The CML drivers have similar benefits to LVDS. These drivers also have a constant level of current, but unlike LVDS, a much smaller number are required due to the serialization of the data. In addition, the CML drivers also offer immunity to common-mode noise since they also use differential signaling.

However, the disadvantage to LVDS and CML is that the current is constant so, even at lower sample rates, the power consumption can still be significant. The advantage over CMOS for converters with higher speeds and resolutions is where power and pin count is significantly reduced when using LVDS or CML.

As converter technology has progressed with increased speeds and resolutions, the digital output drivers have adapted and evolved to meet the requirements necessary transmit data. CML outputs are becoming more popular as the digital output interfaces in converters transition to serialized data transmission.

However, CMOS and LVDS digital outputs are still being used today in current designs. There are applications where each type of digital output is best suited and makes the most sense to use. Each type of output comes with challenges and design considerations and each type of output has its advantages.

In converters with sampling speeds less than 200 Msps, CMOS is still an appropriate technology to employ. When sampling speeds increase above 200 Msps, LVDS becomes a more viable option in many applications as compared to CMOS. To further increase efficiency and reduce power and package size, CML drivers can be employed with a serialized data interface such as JESD204.

About the author
Jonathan Harris is a product applications engineer, High-Speed Converter Group, Analog Devices, Inc. (Greensboro, NC). He has over seven years of experience as an applications engineer supporting products in the RF industry. Jonathan received his MSEE from Auburn University and his BSEE from UNC-Charlotte.

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