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ARM rolls optimization soln's for TSMC 28nm, 40nm process

Posted: 20 Apr 2012 ?? ?Print Version ?Bookmark and Share

Keywords:optimization? 28nm? 40nm? processor-based SoC?

ARM has extended its portfolio of ARM Processor Optimization Pack (POP) solutions for TSMC 40nm and 28nm process technologies. According to the company, at least nine new POP configurations targeting Cortex-A5, Cortex-A7, Cortex-A9 and Cortex-A15 processor cores will be released.

POPs enable ARM partners to quickly close timing of single-, dual- and quad-core implementations across a broad envelope of power, performance and area optimization points, stated ARM. This solution reduces risk and improves time-to-market in the development of Cortex processor-based SoCs with partners achieving competitive results in as little as six weeks, added ARM.

At the 28nm high performance for mobile (HPM) and 28nm high performance (HP) process variants, ARM is launching new POPs for the Cortex-A9 core as well as the first POPs for ARM's Cortex-A7 and Cortex-A15 processors. Since the Cortex-A7 and Cortex-A15 cores are used in tandem as ARM's big.LITTLE energy-efficient processing solution, the addition of POPs for both cores assures a complete solution for big.LITTLE implementations. ARM's lead licensee for the Cortex-A15 POP for TSMC 28nm HPM is progressing toward the tape out of its first chip in the coming months, indicated the company.

ARM Processor Optimization Pack

The expanded lineup of ARM Processor Optimization Pack (POP) solutions target Cortex-A5, Cortex-A7, Cortex-A9 and Cortex-A15 processor cores.

At TSMC 40nm low power (LP), ARM's existing POP offering for the Cortex-A5 and Cortex-A9 processors is being augmented with the new Cortex-A7 POP. In addition, working in concert with TSMC, ARM will offer new POP variants supporting the latest high-speed options for TSMC 40nm LP, so those process options can take full advantage of the POP implementation benefits. ARM's POPs for TSMC 40nm LP for Cortex-A5 (1GHz) and Cortex-A9 (1.4GHz) are shipping in production chips by ARM partners in such applications as smart-TV, STB, mobile computing and smartphones.

A Processor Optimization Pack solution is composed of three elements necessary to achieve an optimized ARM core implementation. First, it contains ARM Artisan Physical IP logic libraries and memory instances that are specifically tuned for a given ARM core and process technology.

This Physical IP is developed through a tightly coupled collaboration with ARM processor engineers in an iterative process to identify the optimal results, noted the company. Second, it includes a comprehensive benchmarking report to document the exact conditions and results ARM achieved for the core implementation. Finally, it includes a POP Implementation Guide that details the methodology used to achieve the result, to enable the end customer to achieve the same implementation quickly and at low risk.

The summary below describes the existing and newly announced POP products for TSMC processes. ARM also incorporates the POP optimizations in hard macros of Cortex cores.





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