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Verification platform geared for SoC, FPGA design

Posted: 20 Apr 2012 ?? ?Print Version ?Bookmark and Share

Keywords:SoC design? FPGA? verification platform?

Mentor Graphics Corp. has made available the 10.1 release of the Questa functional verification platform that according to the company is targeted at transforming the functional verification of complex SoC and FPGA designs. The company added that the solution delivers enhanced support of the Universal Verification Methodology (UVM), accelerated coverage closure and low power verification with Unified Power Format (UPF) support.

The Questa 10.1 release introduces the Questa Multi-Core simulation technology that is targeted for large designs that can take advantage of modern compute systems by partitioning the design to run on multiple CPUs or computers in parallel. This is performed while maintaining a single database for debug and coverage closure. Questa Multi-Core is especially applicable to large designs with long simulation times where users have experienced from 2-5x run time improvement depending on the number of cores used. Additionally, the Questa 10.1 compiler and simulation engine now makes it easier to create a common testbench for use across Questa simulation and Veloce emulation platforms creating a fast path to performance acceleration.

Likewise, the Questa 10.1 platform is the first verification platform with a UVM-aware debug solution that gives engineers essential information about the operation of their dynamic, class-based testbenches in the familiar context of source code and waveform viewing that RTL designers have used for years, said the company. With additional UVM-specific views, Questa 10.1 shows the component hierarchy, class definition tree and other UVM settings specific to a testbench to make it easier to understand the operation of the verification environment.

The Questa Verification Manager is a complete suite of tools that helps manage verification processes, tools and data. At its heart is an updated Unified Coverage DataBase (UCDB), designed specifically to reduce verification file storage needs and improve analysis and query times. Mentor has contributed the UCDB to the Unified Coverage Interoperability Standard (UCIS) driven by the Accellera Systems Initiative. For process and tool management, Questa 10.1 now includes a Run Manager control panel that makes it easier to control, configure, analyze and automate regression environments. Using Questa Run Manager, users have been able to reduce their regression run times from days to hours, noted the company.

To accelerate coverage closure, Questa inFact's intelligent testbench automation generates high-quality, non-redundant stimulus that achieves coverage closure more than 10x faster than any alternative, Mentor Graphics declared. Now with Questa 10.1, users can automatically import their existing SystemVerilog constraints and covergroups, accelerating coverage closure with minimal time and effort. Furthermore, Questa 10.1 now automatically generates SystemVerilog covergroups, simplifying the creation and understanding of coverage models.

Additionally, Questa 10.1 offers support for UPF 2.0, as well as multiple new static and dynamic power checks used for both register transfer level (RTL) and gate level power verification. UPF 2.0 enables support for IP blocks and hard macros, as well as enabling hierarchical composition, which is required to support a power verification methodology that spans block, subsystem and system level. Mentor is taking a leading role in driving the standardization of UPF 2.0 as well as delivering market leading support of this standard.

Mentor Graphics continued by saying that the Questa platform uniquely weaves together leading-edge verification tools with advanced methodologies to help design teams achieve the highest possible verification throughput and measurable design quality.





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