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Design for power methodology: From architectural plan to signoff

Posted: 30 Apr 2012 ?? ?Print Version ?Bookmark and Share

Keywords:system-on-chip? power integrity? register-transfer-language level?

Power is an intimidating challenge for modern system-on-chip (SoC) designs, from both the power consumption and power integrity perspectives. Achieving low-power, from mobile and wireless designs to consumer devices to high-performance networking and computing applications that face power supply and cooling limitations, is now critical to design success. At the same time, rising complexity and chip-level power management techniques make power integrity analysis from chip-to-package-to-system essential. Designing for low-power and power integrity is not automatic C there is no "low-power" button. This article describes a holistic design for power methodology that spans from architectural decisions through front-end design to physical implementation and sign-off.

Figure 1: Design-for-power methodology.

Power is a key challenge in modern IC designs for various applications. The power challenge is comprised of two fundamental aspects: power consumption and power integrity. From mobile and wireless designs where extending battery life is essential to product competitiveness, to consumer devices with package cost constraints, to high-performance networking and computing applications facing power supply and cooling limitations, reducing power consumption is now mission-critical. At the same time, rising design complexity and the use of chip-level power management techniques such as power-gating is forcing design teams to ensure power integrity from chip-to-package-to-system. A modern system-on-chip (SoC) design flow consists of many steps including various levels of abstraction, from system-level and architectural design to detailed physical implementation. Power considerations are important in every step of the design flow, however, only at the high levels of abstraction C at the architectural and hardware design register-transfer-language level (RTL) C are where a significant impact on overall power consumption can be achieved. In order to manage both power consumption and power integrity effectively, design teams must adopt a holistic design-for-power (DFP) methodology, spanning architectural decisions through front-end design to physical implementation and sign-off. A DFP methodology is illustrated in figure 1.

Architectural, hardware/software tradeoffs
Architectural tradeoffs must take into account performance, cost (or area for SoC designs), and power consumption. In addition to this multidimensional design requirement, SoC and system architects must also consider the implications of deploying a particular design function in hardware versus software. Traditionally, these tradeoffs have been performed using spreadsheets and other ad-hoc approaches. While these methods do have a certain amount of utility, a more structured and deterministic solution is needed in this area. As designs grow more complex, a significant portion of the design may be reused from previous generations, so a modeling approach where pre-existing blocks of functional units can be characterized for their power, performance, and area parameters is a key enabler for multidimensional tradeoff analysis.

SoC-level power management techniques
There are several SoC-level power management techniques currently being used and gaining acceptance. One technique is power-gating, or power shut-off. Power-gating means that the power supplies to entire blocks or functional units on the chip can be turned off, resulting in near-zero dynamic and static power consumption. Although power-gating is conceptually simple to understand, design and implementation is quite complex. From the front-end perspective, power supply control signals and their proper sequence need to be designed. During physical design, power supply switches must be carefully placed. Retention, isolation, and level-shifter cells must be used to ensure proper functional correctness of the design, as well as design reliability. In addition to design implementation concerns, it is also important to determine how many power domains are needed, and how many blocks in the design will be power-gated to achieve power consumption goals. While initial analysis may be done with improvised methods similar to those used for architectural tradeoffs, if the design description is available using a hardware description language (HDL) at the RT level of abstraction, then power analysis can be performed for various what-if partitioning scenarios. In addition, once the design power intent is finalized, a common power format (CPF) or unified power format (UPF) file can be created for the downstream design flow implementation.

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