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Design for power methodology: From architectural plan to signoff

Posted: 30 Apr 2012 ?? ?Print Version ?Bookmark and Share

Keywords:system-on-chip? power integrity? register-transfer-language level?

Another important aspect of RTL power reduction is that it must be based on RTL power analysis (i.e., you must measure power before you attempt to reduce it). Analysis-driven RTL power reduction will show that there is often a cost or impact on the design, in terms of leakage power or area, as additional logic gates are used to shut down activity.

A comprehensive set of RTL power reduction techniques must cover all areas of the design: clock / registers, memories, and datapath / control logic. For registers, power reduction is achieved through finding enable conditions for registers not already enabled in the design, as well as improving efficiency (or strengthening) existing enable conditions. There are both combinational and sequential techniques for clock enable generation and strengthening, including XOR-gating (self-gating), forward enable propagation, and observability don't care (ODC).

For memories, power reduction is achieved through detecting and eliminating redundant memory cycles. Often, when memories in the design are selected, the address and read / write control signals are not changing, and yet the memory is continuously clocked. Even though the memory outputs do not change, since the same address location is being read every clock cycle, there is significant wasted power being consumed by the internal circuitry of the memory.

In the control logic / datapath area, it is possible to detect active clouds of logic that are converging on mux inputs, but are not being selected by the mux select signal. It may be feasible to control these logic clouds using the mux select signal, so it is important to identify how much power is wasted in the logic due to this redundant computation.

It is absolutely essential that RTL power reduction techniques are applied following the accurate computation of power consumption and power savings. Because reducing power consumption often involves adding additional logic to turn off logic signals or shut down clocks, the power overhead of this additional logic C both dynamic and static C must be considered. It is not sufficient enough to make RTL power reduction decisions solely based on signal frequencies or activities and duty cycles. Using "blind automation" or a simplistic push-button approach to RTL power reduction may result in a large area and / or timing impact with no actual power advantage.

It is absolutely essential that any RTL power reduction technique be applied following an accurate computation of power consumption and power savings.

Figure 3: Example of power regressions showing a power bug.

RTL power regressions
After RTL coding is completed by the designer it is put through a functional verification cycle. During functional verification processing, while implementing functional engineering change orders (ECOs) or fixing functional bugs, it is possible that power consumption bugs can be introduced. Because traditional functional verification methods do not catch power consumption bugs, and power bugs are not fixed through downstream synthesis of a physical implementation flow, rigorous tracking of power consumption while the design project evolves is required. Similar to functional regressions, this 'power regression' power tracking is shown in figure 3.


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