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Design for power methodology: From architectural plan to signoff

Posted: 30 Apr 2012 ?? ?Print Version ?Bookmark and Share

Keywords:system-on-chip? power integrity? register-transfer-language level?

In order to enable an efficient power regression flow, verification engineers must have access to detailed power data at all times for every run, without repeating the entire power analysis flow. This is possible only if the RTL power analysis tool has a database infrastructure with a user applications programming interface (API) that allows the design team to obtain specific power data and generate custom reports.

Early power integrity, package analysis
With shrinking product life cycles driven by the consumer electronics market, the ability to have as much analysis of the SoC and package / system as possible early in the design flow is critical. It is no longer practical for design teams to wait until the final stages of physical design implementation in order to perform power integrity analysis and select the proper package. Moreover, power-gating switching events can cause a large gradient in the power supply voltage, leading to noise-induced design failures (figure 4).

Figure 4: Power supply gradient caused by a power gating event.

Analyzing power integrity early in the design process is made possible with reliable, accurate, and consistent RTL power analysis technology. This enables design teams to perform early analysis, when RTL simulations that represent functional behavior of the SoC are available. The key challenge with using RTL simulations is that they typically cover tens of thousands, or millions of clock cycles, when in reality only a few critical cycles are needed for power integrity analysis. So having a fast critical cycle selection algorithm is essential. Together with RTL power analysis data and estimated parasitic values, this cycle selection is encapsulated into a compact model representation, which is then analyzed by a sign-off power integrity tool. Early power integrity analysis with RTL power models enables power delivery network planning and estimation of package characteristics C eliminating guesswork and error-prone spreadsheet analysis.

Synthesis and place & route
Synthesis and Place & Route (SP&R) tools transform the design from RTL to gates, perform physical layout, and optimize the design to primarily meet timing and area goals. There are also several power optimization techniques that are available in SP&R tools. Synthesis performs clock-gating at the register level, leveraging register enable conditions. Clock-gating during synthesis is typically done with RTL as input, and produces a fully mapped gate-level netlist. In addition to clock-gating, synthesis tools can perform optimizations at the gate-level for incremental, additional power savings using techniques such as technology mapping and pin swapping. During Place & Route, additional power optimization is done mainly through down-sizing cells or substituting low leakage cells in timing paths where positive slack margin is available. The latter is also known as mixed-Vt (threshold voltage) cell swapping and is an effective technique for leakage power reduction.

Power consumption, power integrity sign-off
The final step in DFP methodology is to ensure that power integrity targets such as dynamic voltage drop are met, guarantee the power intent of the SoC design is preserved, and that the target power consumption is achieved. A highly accurate power integrity and power consumption analysis tool is required for SoC power sign-off. Another key requirement for this step is flexibility of sign-off analysis for various applications. Power delivery network stress tests can effectively employ a vectorless algorithm, while power consumption analysis and specific power integrity analysis for selected conditions can be driven by gate-level or RTL simulations. Gate-level simulations are time-consuming, but the ability to use RTL simulation data for sign-off analysis gives accurate results with fast turnaround times. The sign-off tool of choice must also deliver excellent accuracy against actual silicon measurements.

Power is a formidable challenge for SoC designs, spanning both power consumption and power integrity considerations. In order to tackle this challenge, power must be taken into account very early in the design process, starting with architectural tradeoffs and RTL design, then continuing all the way to sign-off. Designing for low-power and power integrity is not an automatic process C there is no "low-power" button. Instead, power must be considered, analyzed, and managed in every step of the design flow. By following a design-for-power methodology, engineering teams can ensure power is managed in a predictable and consistent fashion, enabling design success.

About the author
William Ruby is the Senior Director of Product Engineering for RTL Power products at Apache Design Inc. a subsidiary of ANSYS. Mr. Ruby has over 20 years of experience in the EDA and semiconductor industry with broad expertise in low-power design. He has served in executive and senior engineering positions at Sequence, Synopsys, Intel, and Siemens. Mr. Ruby holds a B.A. in Physics from University of California at Berkeley, an M.S. in Electrical Engineering from University of Southern California, and an M.B.A from San Jose State University. He was also awarded a patent in high performance memory design.

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