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Boost PMIC performance by optimizing package devt during design

Posted: 30 Apr 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Power management integrated circuits? BGA? QFN?

Nowadays, consumers' expectations of user experience in portable digital devices far exceed the expectations they had just five years ago. Multi-tasking, high-definition video playback and web surfing are just a few of the requirements that can now be achieved on smartphones and tablets.

The power requirements have also increased significantly, whereas in the past the power dissipation was not significant enough to cause concern, the peak power requirements can now reach 10s of Watts and as a result more attention has to be paid to the thermal design and performance of the electronics that go into these portable consumer devices.

Power management integrated circuits (PMICs) or Power management units (PMUs) have evolved over those years and now instead of having to provide output currents of 500mA now have to provide higher and higher output currents.

The package of choice for these devices is typically BGA or CSP, mainly due to the large amount of I/O required. However are these best packages for power? This paper explores the design advantages of using a QFN device as opposed to a BGA device, from both a performance and cost viewpoint and also outlines performance improvements gained over a BGA package.

Considerable design effort is spent in making the functionality of the PMIC meet the requirements of the application processor and surrounding peripherals, but typically the last consideration is the package design. Normally the package is just a way of getting the relevant inputs and outputs out of the silicon to the external world. However, power management design is very susceptible to bad layout, and there are a multitude of application notes which stipulate best practices when placing the external components of any power management circuit. Bad layout and design can affect both performance and efficiency and in extreme causes cause catastrophic failures.

Figure 1: Custom QFN package enables larger power tracks reducing parasitic and improving efficiency.

For its latest family of PMICs Wolfson decided to make the package design a key element in the total development process. By doing this it was possible to maximize the performance of the silicon and to make the best possible device in the smallest size at the lowest cost.

There were three main metrics to improve which drove the design of the QFN over the BGA:

???Efficiency improvement
???Low cost PCB manufacturing
???Reduction of parasitic to improve transient performance
???Efficiency improvement

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