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Boost PMIC performance by optimizing package devt during design

Posted: 30 Apr 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Power management integrated circuits? BGA? QFN?

There are effectively two ways in which the efficiency of the DC-DC is improved by the QFN package. The first is by reducing the parasitic resistance associated with DC-DC converter. Any resistance in the current path adds to the power loss and hence reduces efficiency. The total circuit resistance can be reduced in a QFN, when compared with a BGA due to improved layout and lower package resistance. The improved layout is shown in figure 1, where the power paths for the high-current DCDCs can be much larger than the signal paths, thereby reducing the in-circuit resistance.

The second way in which the QFN improves efficiency is by having a lower thermal resistance (JA). The on-resistance of a MOSFET increases with temperature, therefore for a specified operating condition or power dissipation (Pdissipation) a lower thermal resistance results in a lower junction temperature (Tjunction) as shown by:

Tjunction=JA Pdissipation+Tambient^

where Tambient is the ambient temperature.

Figure 2 shows the efficiency of a PMIC using the same silicon, but one in a BGA package and one in a QFN package.

Figure 2: Comparison of the efficiency of a DCDC converter in a BGA versus QFN.

Low cost PCB manufacturing
The design of the QFN was optimized to ensure it was possible to achieve low cost PCB manufacturing. PMICs are complex devices and this device has four DCDCs, 11 LDOs, GPIOs and a host of functionality to fully control application processors and surrounding peripherals. Therefore it is difficult to produce a low cost solution in a small form factor. The QFN package achieves both low cost and small size, by employing a totally customized design to ensure that the complete solution can be placed on a four layer board, on a single side, with no micro-vias. The low cost 4mil line and 5mil space (track/gap) is achievable as well as 20/12/28 mil PTH (pad/hole/antipad) vias.

Reduction of parasitic
The QFN is optimized to allow the PCB layout to reduce parasitics over a typical BGA or CSP layout. As shown in figure 1 the custom Wolfson QFN allows large printed circuit board tracks for DC-DCs reducing parasitic components which improves performance and increases efficiency.

Fully including the package development in the total PMIC design process results allows circuit designs to provide a low cost, small size, high efficient PMIC solution, with very little compromise. In markets where cost and performance are no longer mutually exclusive it is essential to strive to provide both.

About the author
Dr Jess Brown joined Wolfson Microelectronics in August 2008 and is the Principal Product Line Manager for Power Management, with responsibility for all areas of the product line including product definition, marketing, sales support and product life cycle analysis. He previously worked at Volterra Semiconductor as the European Business Development Manager and prior to that at Vishay Siliconix where he was Mains Powered Power IC Market Development Manager. Dr Brown holds a degree in Electrical and Electronic Engineering from the University of Bath, and a PhD from the University of Sheffield.

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