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A primer on JESD204 standard for ADCs

Posted: 08 May 2012 ?? ?Print Version ?Bookmark and Share

Keywords:analog to digital converters? low-voltage differential signaling? JESD204?

As the resolution and speed of converters has increased, the demand for a more efficient digital-side interface has intensified as well. Currently, analog to digital converters (ADCs) are migrating from parallel low-voltage differential signaling (LVDS) and CMOS digital interfaces to a serialized interface called JESD204, developed by JEDEC (formerly known as the Joint Electron Device Engineering Council).

The JESD204 interface brings this efficiency while offering several advantages over its predecessors in terms of speed, size, and cost. Designs employing JESD204 enjoy the benefits of a faster interface to keep pace with the faster sampling rates of converters. In addition, there is a reduction in pin count, which leads to smaller package sizes and a lower number of trace routes, both of which make board designs much easier and offer lower costs in packaging and board designs.

The standard is also easily scalable so it can be adapted to meet future needs, as has been exhibited by the two revisions which the standard has already undergone. The JESD204 standard has had two revisions since its introduction in 2006 and is now at revision B.

As the standard has been adopted by converter vendors and users, it has been refined and new features have been added that have increased efficiency and ease of implementation. The standard applies to both analog to digital converters as well as digital to analog converters (DACs); however, the focus in this article will be on its application to ADCs.

JESD204 (2006)
In April of 2006, the original version of JESD204 was released. The standard describes a multigigabit serial data link between converter(s) and a receiver, commonly a device such as an FPGA or ASIC. In this version, the serial data link was defined for a single serial lane between a converter or multiple converters and a receiver.

A graphical representation is provided in figure 1. The lane shown is the physical interface between M number of converters and the receiver, where the interface consists of a differential pair of interconnects using current mode logic (CML). The link shown is the serialized data link that is established between the converter(s) and the receiver. The frame clock is routed to both the converter(s) and the receiver and provides the clock for the JESD204 link between the devices.

Figure 1: JESD204 original standard.

The lane data rate is defined between 312.5 Megabits per second (Mbps) and 3.125 Gigabits per second (Gbps) with both source and load impedance defined as 100 ? 20%. The differential voltage level is defined as being nominally 800 mV peak-to-peak with a common-mode voltage level range from 0.72 V to 1.23 V. The link utilizes 8b/10b encoding which incorporates an embedded clock, removing the need to route an additional clock line, and the associated complexity of aligning an additional clock signal with the transmitted data at high data rates.

This form of serial data transmission allows the trace-to-trace tolerance to be relaxed, relative to synchronous-sampling parallel LVDS and CMOS interface designs. In addition, the encoding is DC balanced, which guarantees a significant transition frequency for use with clock and data recovery (CDR) designs.

The encoding also allows for the use of data and control characters which specify link alignment, maintenance, and monitoring. The standard specifies training patterns with these control characters that allow the lane to be aligned between the converter(s) and the receiver across the link.

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