Multi-rate 100GbE PHYs target data centers, core networks
Keywords:CMOS? physical layer transceivers? PHYs? networks?
The PHYs' low-power 40nm CMOS architecture dissipates only 2.5W per port, saving 35 percent of the power used by previously available solutions. The BCM84790 comes in a 17mm x 17mm BGA package that supports CFP network applications. The BCM84793 comes in a 19mm x 19mm BGA package with the ability to support 10-lane bi-directional transmissions at 10Gbit/s each. This added flexibility ensures support for future-generation networking formats such as CFP2 and CXP.
The gearbox PHYs can multiplex and demultiplex data across four 25Gbit/s channels to (or from) ten 10Gbit/s channels, making them suitable high-bandwidth datacenter and enterprise networks. They can also be configured to support four bi-directional lanes at 10Gbit/s for 40GbE repeater applications, support Ethernet and optical transport networking, and are compliant with the IEEE 802.3ba standard for 100GbE and ITU OTL 4.4 signaling.
The PHYs support Ethernet and optical transport networking; feature 100GbE/OTN VSR28 to CAUI interface; and have less than 200fs rms of random jitter on the 25Gbit/s transmit outputs. They offer high-speed eye monitoring diagnostics on all data I/O, and integrated clean-up PLL to cut BOM. Plus, they have single REFCLK (reference clock) input and low latency architecture.
The BCM84790 and BCM84793 are sampling now. Production release is scheduled for 2H 2012.
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