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Prototyping system enhances debugging capability

Posted: 11 May 2012 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? SoC designs? debug system?

Users of Synposys Inc.'s HAPS FPGA-based prototyping systems can now make use of a Deep Trace Debug feature that is said to enhance capacity and fault isolation capabilities of the system as well as free up on-chip FPGA memory required for validating complex SoC designs. The feature can use 100 times more signal storage capacity than the traditional memory storage employed by on-chip FPGA logic debuggers

To confirm the functionality of high-speed interface designs, it is necessary to sample for several milliseconds at dozens of frequencies at a time. Designers have had to choose between capturing long signal trace histories that use up FPGA memory resources or save FPGA memory resources but lose detailed visibility into signal trace history.

By using Synopsys' Identify Intelligent Integrated Circuit Emulator (IICE) with a HAPS Deep Trace Debug SRAM daughter board, HAPS Deep Trace Debug enables many unique signal probes with complex triggers to be recorded and provides deeper memory to store extensive state history as the system executes. The SRAM daughter board also frees up the FPGA's on-chip RAM for prototyping an SoC design's memory blocks.

HAPS Deep Trace Debug support in Synopsys' Identify RTL debugger software and HAPS Deep Trace Debug SRAM daughter boards is available immediately.





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