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Quick fix for pesky FPGA design errors

Posted: 16 May 2012 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? hierarchical? ASIC?

Preparing the first implementation of an FPGA design on the board used to be relatively straightforward, requiring only a single design project, a handful of source projects, and a single design engineer. Subsequent improvements to the FPGA design on the board could be reflected in a matter of hours.

Today's designs are not so simple. FPGAs are used in production to implement complex designs such as those for consumer, computer, and communications applications, where staying ahead of the competition requires fast delivery of the next-generation system that includes new functionality or perhaps takes advantage of a new FPGA device.

More and more, FPGA-based prototyping systems are being used to verify huge pending ASIC designs. These types of designs typically consist of 1000s of source files and implement the equivalent of multimillion gate ASIC designs. To add to the problem, the engineer implementing and verifying the design in an FPGA may not have been the one who authored the RTL code and may therefore be unfamiliar with it.

Some FPGA systems are partitioned across multiple FPGAs, adding another level of complexity to the process. With designs this huge and design source often foreign to the user, the time required to bring up the first working implementation of the design on the board can now be weeks, the result of a staggering number of setup requirements, ASIC design conversion issues and user errors in the overall design specification.

Users hope for quick feedback on their design specification C that is, efficient ways to identify, isolate and fix issues that prevent design completion from occurring. The fewer design iterations needed to do this, the better. Whereas top-down implementation methodologies still work well in some cases, a hierarchical design methodology is usually more appropriate for runtime and design stability reasons.

But, that's only one piece of the puzzle. Another important piece is the ability for the design project to proceed in the presence of errors using synthesis "continue-on-error" technology, and then merge multiple fixes at once, incrementally, using hierarchical design approaches. By using these methods users can find multiple errors in one design iteration and apply fixes in parallel, potentially cutting days, if not weeks, off the time taken for initial board bring-up. Let's explore this in more detail.

Challenges for FPGA design bring-up
Designers face several technical challenges during initial board bring-up of their FPGA-based system as follows:

???Large projects being imported from non-FPGA environments are initially hard to set up for successful FPGA synthesis and verification. There may be ASIC design conversion issues, for example with clocks and memories. The design may simply fail to compile during synthesis due to ASIC gated clock conversion failure or because some of the ASIC source is missing.
???Determining the block(s) responsible or the root cause of a design failure on the board is difficult
???Comprehending the design hierarchy and file interdependencies, especially if one did not author the source files, can be a challenge, making it hard to isolate a module to analyze and improve it
???FPGA designs consisting of more than one FPGA add additional levels of complexity because the user must now ensure that inter-chip signal and clock synchronization occurs between the FPGAs on the board

Need for hierarchical "divide-and-conquer" flows
Hierarchical flows can help with all of these design challenges. With the ability to divide large projects into hierarchical blocks that can be treated as individual subprojects, the designer can focus on improving or debugging a smaller problem and isolate suspected errors to individual blocks or modules of the design.

This can be useful in assessing both design compilation errors and in determining the reason why the design does not work properly on the board. FPGA board bring-up problems may be the result of erroneous clocking setup. This kind of issue can also be identified by dividing the design up into blocks and running simple testbenches at the block interface level.

Tool efficiency is a must
While hierarchical design can help the design and debug process, it's the tools and tool features that implement the theory of hierarchical design on the board. To take advantage of the benefits that hierarchical design can offer, users must choose tools that incorporate key productivity features to identify, isolate, and correct design errors quickly.

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