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EDA solutions claim 50% cut in time-to-closure

Posted: 17 May 2012 ?? ?Print Version ?Bookmark and Share

Keywords:EDA solutions? analog/mixed-signal?

ICScape Inc. brings to the global market EDA solutions that, according to the company, are silicon-proven, scalable and capable of a 50 percent reduction in time-to-closure.

ICScape's design closure solutions are: the physically-aware timing ECO tool, TimingExplorer; ClockExplorer, which automates complex SoC clock analysis and optimization; Skipper, a high-capacity and ultra-fast integrated chip finishing solution; and FlashLVL, the fastest layout versus layout comparison (XOR) tool. The products are customer and silicon-proven using a variety of process technologies, including 28nm.

ICScape, by virtue of its May merger with Huada Empyrean Software (HES) in China, has expanded its offerings to include the acquired technologies, including an analog/mixed-signal product line. They are: Aether (OpenAccess based custom IC design platformschematic and layout editors), Aeolus (circuit simulator), iWave (waveform viewing and analysis), Argus (physical verification), PVE (physical verification debugger) and RCExplorer (RC extraction and analysis that can be used in all design stages).

ICScape's tools have enabled over 100 tapeouts across a variety of applications areas, including: storage, wireless, baseband, data communications, multimedia, graphics, chipset and power management design. The designs span a variety of process technologies, including 28nm.

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