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IP subsystem eases SoC dev't for SSD apps

Posted: 18 May 2012 ?? ?Print Version ?Bookmark and Share

Keywords:SoC development? SSD apps? design IP?

Cadence Design Systems Inc. has unveiled an IP subsystem designed for the development of SoCs that support the NVM Express 1.0c interface technology standard for the SSD market. The solution integrates the Cadence Design IP for NVM Express controller and Cadence Design IP for NVM Express subsystem. The subsystem features component IP including the NVM Express Controller, firmware, and the corresponding NVMe and PCIe models from the Cadence Verification IP Catalog.

The NVM Express specification is expected to speed the adoption of PCIe-based SSDs because it is said to improve performance and cut power consumption and latency compared to existing SATA/SAS interfaces or proprietary PCIe implementations. The NVM Express specification defines the register interface, command set, and feature set to provide a scalable interface for PCIe-based SSDs.

The controller used in the Cadence NVM Express solution supports advanced command management, data tiering and hardware command acceleration. The IP is highly configurable, allowing it to target the broad scope of applications possible with NVM Express. The included driver firmware offers an easy interface to the system firmware. The solution also includes a verification and test environment spanning from the PCIe interface to the internal bus fabric.

Cadence offers a design methodology that uses the Cadence Virtual System Platform, NVM Express and PCIe verifications models, Cadence Incisive Software extensions and flash memory models to accelerate the design and integration of the Cadence NVM Express IP solution. These components provide a scalable verification and test platform for system-level software and hardware development and testing.

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