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PCM progress report no. 2: Review of PCM-related activities in early 2011

Posted: 11 Apr 2011 ?? ?Print Version ?Bookmark and Share

Keywords:phase change memory? carbon nano-tubes? Write-erase lifetime?

Last month, EETimes [1] reported on the study tackling low power phase change memory (PCM) devices. Workers at University of Illinois Urbana-Champaign have reported their results for phase change memory (PCM) devices formed by creating narrow 20C30nm gaps in 3nm diameter carbon nano-tubes (CNTs) and opened some new directions for further investigation [2].

Current density
While the authors [2] comment optimistically on fabricating low power PCMs, there is no discussion of current density. They describe their "best" results, obtained from PCM devices with set/rest currents of 1uA/5uA respectively with 3V across a 20-30nm gap and their stated carbon nano-tube diameter as 3nm. Assuming that the contact is solid planar, the contact current density calculates as

J = 7 x 10+7 Amps/sq-cm.

The authors [2] report higher values of reset currents 8uA, for what as described as not their "best" devices, for unspecified reasons, increasing the calculated current density value (J) to ~1 x 10+8 A/sq-cm. If the electrodes are truly tubular, as illustrated in figure 1(a) and the notional contact is as shown, the contact current density is likely to exceed this value. Even if the region of molten chalcogenide penetrates into and around the end of the CNT tube during reset, enlarging the contact area as illustrated in figure 1(b), the total contact area will still involve only a few hundred atoms.

Figure 1: Diagram showing two cutaway views of one electrode of a carbon nanotube (CNT- PCM, (a) the notional contact area of an annulus of atoms,(b) cutaway section CNT-PCM during reset.

Atomic force microscope (AFM) evidence from [2] appears to show a flat spherical shaped region of active material equal to about 2 to 3 diameters, approximately the gap width. This suggests the molten region may not extend very far into the CNT. As well as the active region, the calculated levels of current density will have a deleterious effect on other components in an array and that is already one of the serious and ongoing PCM problems.

With respect to current density, there is now good evidence [3], summarized by this author in [4] that during reset the molten GST material acts like an electrochemical cell (plating bath) and it is that process that accounts for element separation, composition change and eventual failure. Therefore an argument might be made that an emphasis on current density as the "villain in the piece" for the memory device, especially for the very small contact area of the CNT-PCM devices might be misplaced. Current density is in effect the signature of the presence of the "electrochemical cell" plating voltage, with the former necessary to maintain a very small volume of chalcogenide in a molten state.

Write-erase lifetime
The authors [2] suggest that they were able to get 200 write/erase cycles from the carbon nano-tube devices. Their write/erase cycle time set/reset was 150/50ns. Add to that some read verify time it would not take long to reach 1000+ cycles. So, it must be assumed 200 cycles was somewhere close to a maximum.

What would be more important to know is was the predominant failure on state or off state? One of the key pieces of information provided that might be significant to the observed write/erase lifetime is the fact that all devices were reported by [2] as having very similar "on" state resistance. An explanation of this might be the domination of the total resistance of the "on" state by the spreading resistance of the very small contact area between the two ends of the 3nm CNTs and the crystallized region. Examination of the micrographs [2] suggests that the active region is of a flat spherical form.

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