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PCM progress report no. 7: A look at Samsung's 8-Gb array

Posted: 28 May 2012 ?? ?Print Version ?Bookmark and Share

Keywords:PCM? 8-Gb array? LPDDR2-NVM?

At ISSCC2012, Samsung has presented their 8-Gb PRAM [1] with several features that seem to be worth discussing. Meanwhile, phase-change memory (PCM) watchers wait for the other shoe to drop in the form of a possibility of an associated PCM product announcement.

The architecture of Samsung's 8-Gb array, from the top down to the individual PCM cells runs as follows: eight partitions of 1 Gb, each of which is divided into 128 sub-arrays (tiles), organized as a matrix of 4096 word lines (WLs) by 2048 bit lines (BLs). WL strapping contacts are situated at 64-cell intervals, which the authors assert provides a 19% area gain in over earlier 1 Gb work [2] in addition to the advantages introduced by moving from 58-nm to 20-nm technology. The result is a 9.43 x 6.30 mm2 chip. The device operates at 1.8 V and uses a low power, double-data-rate non-volatile memory (LPDDR2-NVM) interface. No quantitative data on chip power dissipation was provided.

Write bandwidth
Although the headline write bandwidth claimed for the 8-Gb array was 40 MB/s, under certain conditions this could be increased. The array architecture employed parallelism to increase the bandwidth over the Samsung's earlier 1-Gb demonstration array [2]. Parallel write operation, upped to 128bit from the 32bit of the earlier 1-Gb array, provides the increased bandwidth. There was an indication that when the device was optimally implemented, this could be increased to 133 MB/s. To understand in part how that is possible, it is necessary to explore the form of the write/erase (w/e) pulse. Pulse shaping of the leading and trailing edges and multipulse trains has long been a feature of PCM development, usually in order to optimize a particular device characteristic such as w/e lifetime, on/off resistance ratios or values, and elevated temperature data retention characteristics.

Figure 1: Features of the programming pulses illustrate how pre-emphasis reduces rise time and contributes to reducing total pulse width.

For their 8-Gb array, the Samsung team brings something new to the PCM table in the form of the write pulse presented to the PCM cell. By design, the pulse that is delivered to the cell is formed in part by the parasitic resistance and capacitance of the array. The write pulse uses what is described as "pre-emphasis" technique (figure 1). In this approach, the write generator produces a pulse output in which the initial period of the pulse is of greater amplitude than is actually required to reset or set the device. This pre-emphasis pulse is then integrated by the parasitic capacitance and resistance of the word and bit lines to produce, at the PCM cell, a leading edge with a rise time to the required current that is significantly less than would be the case if pre-emphasis was not used. The net effect is to reduce the overall write time.

Other effects that increase the write time, shown as TA and TB in figure 1, are there to allow the high-voltage programming charge pump to recover. The reason they are not lumped together is because while charge pump recovery is the main purpose, the authors state that it is not the only role. I would suggest that other roles might be to allow for the thermal recovery of the PCM cell and to allow discharge of all of the parasitic capacitance. The latter is especially important when the passive parasitic parts of the array are used for pulse shaping.

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