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32bit DSPs power mobile audio, voice apps

Posted: 29 May 2012 ?? ?Print Version ?Bookmark and Share

Keywords:DSP? audio apps? voice apps?

Ceva Inc. launches a 32bit DSP architecture framework for audio and voice applications. The low-power and scalable CEVA-TeakLite-4 is designed to handle voice pre-processing and audio post-processing algorithms and multichannel audio codecs. It is suited for smartphones, mobile computing and digital home devices.

The architecture framework introduces smart power management technology and supports customer-owned extensions, making it flexible and suitable area- and power-sensitive designs. It claims to consume up to 25 percent less die area and requires up to 30 percent less power than the previous generation CEVA-TeakLite-III DSP for decoding MP3 with Dolby Mobile 3+ post-processing.

The 32bit CEVA-TeakLite-4 DSP architecture directly addresses the challenges faced by the semiconductor industry in enabling high-quality audio and voice performance in all types of devices. To deliver better voice intelligibility in noisy environments for example, advanced pre-processing technologies reduce the background noise and improve voice clarity, requiring support for computational-intensive algorithms. Likewise, the transition to wideband voice codecs for VoIP and voice-over-LTE (VoLTE) applications requires significantly more DSP horsepower than traditional narrowband voice codecs used today. And in mobile and home entertainment devices, audio post-processing improves consumer experience, delivering virtual surround sound, speaker correction, bass expansion effects, and more. The processing required to deliver this level of performance is significantly more complex than what can be efficiently achieved with 16bit and 24bit DSPs utilized today, bringing 32bit audio processing to the forefront.

First four cores

The CEVA-TeakLite-4 architecture is initially available as a series of four compatible DSP cores, offering designers a range of application-specific cost/performance alternatives to meet their application requirements.

The CEVA-TL410 and CEVA-TL411 DSPs offer single and dual 32x32 bit multipliers, respectively, targeting voice and audio codecs and hubs. Meanwhile the CEVA-TL420 and CEVA-TL421 DSPs offer additional fully cached memory subsystems and AXI system interfaces, targeting application processors and home audio SoCs.

Courtesy of a variable 10 stage pipeline, the CEVA-TeakLite-4 architecture scales from an area-optimized implementation of less than 100K gates and ultra-low power consumption, up to a 1.5GHz implementation at 28nm for high-end SoCs. All CEVA-TeakLite-4 DSPs leverage Ceva's second generation Power Scaling Unit (PSU 2.0) which dynamically supports clock and voltage scaling with finer granularity within the processor, memories, buses and system resources.

The CEVA-TeakLite-4DSPs are supported by CEVA-Toolbox, a complete software development environment, enabling the entire architecture to be programmed in C-level. An integrated simulator provides accurate and efficient verification of the entire system including the memory subsystems. In addition, CEVA-Tool-box includes libraries, a graphical debugger, and a complete optimization tool chain named Ceva Application Optimizer. The Application Optimizer enables automatic and manual optimization applied in the C source code.

The first members of the CEVA-TeakLite-4 DSP family will be generally available for licensing in 2Q and 3Q12.

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