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FPGAs boast high density for wired, wireless communications

Posted: 13 Jun 2012 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? SERDES? DSP blocks?

Lattice Semiconductor Corp. has begun shipping the LatticeECP4-190 FPGA, the highest density member of the company's ECP4 family of low cost, low power mid-range devices under 200K LUTs.

The LatticeECP4-190, features 183K LUTs, 480 DDR DSP multipliers (18x18), 5.8Mbits of memory and twelve 6Gb/s SERDES channels. Available in flip-chip packages with 676-, 900- and 1152-pins, it is suited for cost- and power-sensitive wireless, wireline, video and computing applications

The LatticeECP4-190 FPGA offers high-speed CPRI and SRIO 2.1 interfaces and DDR DSP blocks for building heterogeneous wireless networks. It also provides wireline access developers with 36 embedded clock and data recovery (CDR) circuits to build high port density switches and routers using innovative low cost, low power FPGAs. The powerful DSP blocks and a growing portfolio of third-party IP cores and reference designs are also enabling video and surveillance camera customers to implement complex algorithms using affordable, mid-range FPGAs.

Select customers have early access to Lattice Diamond 2.0 beta design software and can begin to design and program their new samples immediately. The software offers designers a power calculator, a pin-based simultaneous switching output noise calculator and proven MAP and PAR FPGA implementation algorithms that help ensure low cost and low power design solutions.

The LatticeECP4-190 silicon and Lattice Diamond 2.0 beta software have been released to select customers developing market-leading solutions. The price for the LatticeECP4-190 device in the 676fcBGA package in 100K unit volumes will start at $60 for delivery in 2H13.

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