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Managing power islands on chips

Posted: 18 Jun 2012 ?? ?Print Version ?Bookmark and Share

Keywords:multiVT transistors? power-aware emulation? circuit simulation?

Performance is now out of the spotlight as power is now on focus. Yes, speed still matters, and, especially in mobile applications, we have not yet reached that desktop level of "good enough." So there's more work to do to make mobile devices faster, even as more duties are piled on.

However, people won't buy a phone that they have to recharge every couple hours, no matter how fast it is. So it's fair to say that power has to be consulted before performance gets to have its way. And the search for power savings has now affected every level of the design hierarchy. It used to be pushed down to the circuit designers, but low-level techniques, like the use of multiVT transistors and clock gating, bring only moderate gains in the power struggle.

The real game is now at the system level, and this involves software as well as hardware. In particular, the ability to shut off parts of the circuit when not in use has become an important consideration. In fact, there's been something of an attitude shift in some quarters: instead of starting with an "everything on" default, and turning things off when you can, start with an "everything off" assumption and turn on only what you need.

Regardless of which of these angles you take, you end up with power "islands" on the chip that can be on or off, and control of the power state can be set either by hardware or software (either low-level firmware or even an application). This reflects an endpoint in the ongoing trajectory away from monolithic power. And it adds new verification challenges, especially at the emulation stage, when an SoC is being validated before the actual chip circuitry may be complete.

Moving to the islands
Chip designers are taught some basic assumptions when designing fundamental circuits. Key amongst them is that VCC (or VDD, depending on whether your pedigree includes bipolar junction transistors) and ground are connected. This is particularly important for digital design. Analog designers are used to having to pay attention to every detail short of the phase of the moon, but digital design is all about abstraction. And abstraction involves assumptions.

The assumption that power and ground are connected is critical to logic synthesis and design at the behavioral level. If you break that assumption without telling anyone, diodes that should block electrons stop blocking, and currents that you never expected can wreak analog havoc on the otherwise clean, Boolean design. With a monolithic power structure, you can assume that if power and ground aren't connected, nothing will work, and no one will be surprised.

Figure 1: The move from monolithic power to multiple power islands. Many islands now share the same voltage, but must be independent so they can be powered down.

So the move away from a single power/ground setup came cautiously, and was first motivated less by power and more by the need for different voltages in different parts of the circuit. I/Os in particular needed to support higher legacy voltages even as the core voltages dropped. Power did play into the decision as higher voltages were allocated to blocks that were in the critical path, with relaxed voltages for other parts of the chip.

Interfacing different domains with different voltages presents obvious risks. It's not just a matter of paying attention to what happens when a block is on or off; even with everything running, you have to protect against "leakage" (or "floodage") from one power domain to another. Level-shifting and isolation go together to make sure that all the different power levels can cohabitate.

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