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Managing power islands on chips

Posted: 18 Jun 2012 ?? ?Print Version ?Bookmark and Share

Keywords:multiVT transistors? power-aware emulation? circuit simulation?

Figure 2 shows how this can be managed for an island that's powered down. Because the internal core logic of the powered-down block is assumed to be effectively isolated from the rest of the chip, only the peripheral registers matter; their values are then corrupted (represented by "C" in the figure). For a given application, the designer may have a more precise sense of what the powered-down values will be, so he or she should have some control over how the corruption is implemented.

Figure 3 shows a similar circuit while powering up or down. The abiding assumption here is that nothing is known, neither in the periphery nor the core of the block. But the worst case would be where the periphery is still active, sending on the results of the logic in the core, which is in an indeterminate state.

Figure 2: A powered-down island assumes an isolated interior and corrupted periphery.

Figure 3: An island in power transition has an active periphery and a corrupted interior.

The solution here is to corrupt the core register values while leaving the periphery in an active state. As with the prior case, it must be possible to override the corrupted assignments when more is known about what the actual values will be.

With this capability in place, a verification engineer can now run multiple power cycles, using different corrupt values, to build confidence that the circuit is robust in the face of these changes. But even more powerful is the fact that an emulator with this capability can simply run the target software, and, at the direction of a UPF file, all power island changes and the isolation tests will automatically occur, further building confidence in the quality of the design.

The existence of these powered-down islands is only going to increase, especially as "powered off" becomes the default instead of "powered on." Using power-aware emulation to verify the logic-level robustness of an SoC in the face of power changes, before actual circuits may be in place, is likely to become as commonplace as logic verification itself.

About the author
Ludovic Larzul is one of the founders of EVE and the vice president of engineering. He has close to 20 years of engineering and management experience in the EDA industry. Through his leadership, EVE developed seven generations of emulation platforms, capturing a leadership in hardware/software co-verification. Ludovic previously served as principal engineer in the emulation division of Mentor Graphics and worked for Alcatel on telecommunication switches. He holds a Diplome d'Ingenieur de l'Institut de Recherche et d'Enseignement Superieur aux Techniques de l'Electronique (Ecole Polytechnique de Nantes).

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