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Handling behemoth designs

Posted: 20 Jun 2012 ?? ?Print Version ?Bookmark and Share

Keywords:hierarchical? place and route? verification? DFM?

If we consider the IC design trends of the past 20 years as an example, we will likely be required to implement a trillion transistors or more on a chip in the next 10 years. Even at 20nm, chip sizes touching billions of transistors present the age old, perpetually unanswered problem of how to most efficiently implement a design of staggering magnitude. Do you do it flat or hierarchical? Are your decisions based on the current tool capabilities or limitations? Is the design being implemented across geographies or locally? Is it a complex SoC or an ASIC? Do you have any 3rd party IPs or analog components? Is the market window three months or three years away? Do you have a fixed area or power budget that must be met?

Tools and methodologies for the physical implementation of these big designsfrom synthesis through place and route, verification, and DFMhave typically used either a purely flat implementation, or a hierarchical implementation. Both the approaches have advantages and disadvantages (table), but have worked reasonably well until the recent move to 20/14nm. At these advanced nodes, the current tools and methodologies seem to be running out of steam and the design community is looking for a solution that addresses the performance, complexity and time-to-market requirements while also handling large amounts of data.

Table: A summary of the advantages and disadvantages of hierarchical and flat flows.

In this article we discuss some strategies and tool requirements for physical implementation of such large and complex semiconductors. We make a case for a hybrid design methodologya pseudo-flat flow that uses existing tools, technology, and design team infrastructure to enable better results in less time than the traditional flows.

Flat design flows
Flat flows have been in vogue since the early days of IC design and for good reasons C it is a straightforward flow that provides the best QoR (quality of results) in terms of design utilization and performance. The full design is implemented as one entity and typically owned by one engineer. Figure 1 illustrates how a design is viewed in a flat flow.

Figure 1: A view of a design in a flat design flow. All the design information for blocks and the top-level logic is available to the place and route tools. This is good for creating block budgets, assigning pins, and optimizing, but bad for memory footprint, runtime, and ECOs.

The flat flow starts with pad placement followed by macro placement and fast prototyping. Once the power and ground grid is inserted, the design goes through a few iterations of physical synthesis, cell placement legalization, and then through clock tree synthesis (CTS) and optimization. The next step is detail routing and more optimization. Finally, design closure, which takes into account signal integrity and lithography design variability affects. At this point, all the requirements of the design, such as power consumption, timing, performance, area, and manufacturability, must converge. That is, you must meet all those requirements.

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