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FPGA design software upgrades 28nm device support

Posted: 15 Jun 2012 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? design software? Qsys system integration?

Altera Corp. launches the Quartus II Software v12.0, the latest version of its development software. The FPGA design software claims to provide customers with 4X faster compile times for 28nm designs.

The software upgrades 28nm device support, including initial support for Altera's SoC FPGAs; enhances Qsys system integration and DSP Builder tools; and offers an improved IP core

Quartus II software v12.0 maintains the industry's fastest compile times, allowing customers to focus design team resources on innovating their designs while maximizing designer productivity. Stratix V FPGA users will achieve on average a 35 percent reduction in compile times, while Cyclone V and Arria V FPGAs users will see on average a 25 percent reduction in compile times with this software version, as compared to the company's previous software release.

Customers can select and start designing a wide range of low-cost, mid-range and high-end 28nm FPGAs. New support includes the following:

  • Programming support for Stratix V GX and Stratix V GS production devices, including 5SGXA7, 5SGXA4, 5SGXA3 and 5SGXA5. As well as 5SGSD5 and 5SGSD4
  • Programming support for Stratix V GT FPGA 5SGTC5
  • Device support for the largest Arria V GT FPGA 5AGTD7 with final pin-out
  • Device support for Cyclone V FPGAs 5CEA7 and 5CGTD7. As well as 5CEA9, 5CGXC9 and 5CGTD9
  • Compilation support for Cyclone V SX SoC FPGA5CSXFC6D6

AXI-3 interface support
With this release, Altera is adding support for the ARM AMBA AXI-3 interface in its Qsys system integration tool, giving users the flexibility to connect IP cores and IP subsystems based on different standard interfaces. Qsys claims to be the first system integration tool based on network-on-a-chip (NoC) technology and giving users a high-performance interconnect. The tool eases system development by integrating IP functions and IP subsystems using a hierarchical approach. The latest release includes several new ease-of-use features that provide additional automation to system designers and simplifies design reuse.

Additional Features in the Quartus II Design Suite Include:

  • New DSP support with DSP Builder�v12.0Communicates with DDR memories from MATLAB via System Console and uses new floating-point functions for improved design productivity and greater DSP efficiency.
  • Improved Video and Image Processing (VIP) Suite and Video Interface IPEases development of video processing applications through an updated Scaler II MegaCore function with edge-adaptive algorithm and new Avalon-Streaming (Avalon-ST)�Video Monitor and Trace System IP cores.
  • Enhanced Transceiver Design and VerificationUpdated transceiver toolkit support for Arria V FPGAs and support for higher speed transceiver data rates (up to 14.1Gb/s in Stratix V FPGAs).





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