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Reference flow pushes low power design

Posted: 29 Jun 2012 ?? ?Print Version ?Bookmark and Share

Keywords:reference design flow? IC tool suite? chip design?

Synopsys Inc. has released version 5.0 of its 40nm RTL-to-GDSII reference design flow. The SMIC-Synopsys Reference Flow 5.0 incorporates a range of automated low power and high-performance capabilities through Synopsys' entire tool suite. It gives designers differentiated performance and power results needed for today's chip designs.

A collaborative work by SMIC and Synopsys Professional Services, the reference flow features new design techniques such as automated clock mesh synthesis to increase performance and responsiveness of a SoC. It also features a gate array engineering change order flow that enables designers to achieve design closure without having to start from scratch with a redesign. The reference flow also includes support for low power techniques such as power-aware clock tree synthesis, power gating and physical optimization, driven by the IEEE 1801 low power design intent standard.

The SMIC-Synopsys Reference Flow 5.0 is available now.





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