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Optimizing FPGAs for low power apps

Posted: 17 Jul 2012 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? HPL process? DSP?

Power has become a key factor in the ever-important search for the "perfect" FPGA for a given design. Power management is critical in most applications. Some standards specify maximum power per card or per system. As such, designers must consider power much earlier in the design flow than ever beforeoften starting with the selection of an FPGA.

Reducing the power consumption of the FPGA simplifies the board design by lowering the supply rails, simplifying power supply design and thermal management, and easing the requirements on the power distribution planes. Low power also contributes to longer battery life and higher reliability (cooler-running systems last longer) of the system.

Power challenges
With each generation of process technology, transistors are becoming smaller and smaller in accordance with Moore's Law. This phenomenon has the unfortunate side effect of incurring more leakage within each transistor, which leads to higher static power consumptionthat is, the amount of current an FPGA draws when not operating. Increased FPGA performance drives the clock rate higher, which leads to higher levels of dynamic power. Where static power is driven by transistor leakage current, dynamic power is based on the switching frequency in the programmable logic and I/Os. Exacerbating both types of power consumption, FPGAs are growing in capacity with each product generation. More logic means more leakage and more transistors operating at higher speeds per device.

Because of these issues, designers must be more aware of their power supply and thermal-management issues earlier in their design cycles. Slapping a heat sink over a device may not adequately resolve these issues. Instead, designers must look for opportunities to reduce the logic in the design.

Let's take a look at some guidelines that will help you understand what type of action to take at various points in the design cycle to reduce the power consumption of an FPGA design. Clearly, having a thorough understanding of these issues early in the design process will yield the greatest reward.

Figure 1: The different points in the design cycle, from FPGA selection through low-power design techniques.

7 series process technology
During FPGA selection, carefully consider the process technology, which helps you identify the leakage and performance of the device. The Xilinx 7 series FPGAs are based on the 28nm High-Performance, Low-Power (28 HPL) process, covering the high-performance space while also enabling significant power reduction. Choosing devices built on the lower-leakage HPL process eliminates the need for complex and expensive static-power-management schemes in an FPGA design.

FPGAs built with the 28 HP process have no performance advantage over 7 series FPGAs, while some other, competing FPGAs come with the severe penalty of more than twice the static power and present challenges in reducing leakage. Figure 2 shows a holistic power reduction approach for the 7 series family, which has half the overall power consumption of prior-generation, 40-nm FPGA devices.

Figure 2: Xilinx 7 series FPGAs consume half the power of devices built in the earlier 40-nm process.

Designers can choose a larger FPGA for purposes of development and later migrate to a smaller one in their production line. Choosing a smaller FPGA will not only bring down the cost but will also reduce the power consumption of the system.

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