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Latest IP core offering from Altera reduces design complexity

Posted: 12 Jul 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Ethernet? IP core? FPGA?

Altera Corp. has announced the production availability of its 40Gbit/s Ethernet (40GbE) and 100Gbit/s Ethernet (100GbE) intellectual property (IP) cores. These cores are effective for building systems requiring very high throughput-rate standard Ethernet connections, including chip-to-optical module, chip-to-chip, and backplane applications. The media access control (MAC) and physical coding sublayer plus physical media attachment (PCS+PMA) sublayer IP cores are IEEE 802.3ba-2010�standard compliant,�reducing design complexity for customers integrating 40GbE and 100GbE connections on Altera's 28nm Stratix V FPGAs and 40nm Stratix IV FPGAs.

Subsystem IP, including 40GbE/100GbE MAC and PCS+PMA layers, becomes a vital component in the system design team's toolkit as more system designs use Ethernet at high speeds both for local area network attachment and to interconnect within systems. These cores, optimized for integration with Altera development kits and Altera's Quartus II software v12.0, create high-performance, low-cost, subsystem IP in Stratix IV and Stratix V FPGAs.

The 40GbE and 100GbE MAC and PHY IP cores provide an interface composed of a single packet-based channel that is logically compatible with previous-generation Ethernet systems. The cores are supported in Altera's Stratix V GT and GX FPGAs with transceivers operating at data rates up to 28.05Gbit/s and 14.1Gbit/s, respectively and Stratix IV GT FPGAs with transceivers operating at data rates up to 11.3Gbit/s. By combining high density, high performance and a rich feature set, Stratix FPGAs allow customers to integrate more functions and maximize system bandwidth.

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