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Multitest platform tests partially stacked dies

Posted: 12 Jul 2012 ?? ?Print Version ?Bookmark and Share

Keywords:electrical testing? SoC (system-on-chip) devices? bare dies?

An integrated setup from Multitest enables the electrical testing of partial stacks during the assembly of SoC (system-on-chip) devices. The platform consists of an InStrip3D handler, a test interface board and vertical-spring contactor. According Multitest, the system ensures reliable contacting yield and only requires minimum contact force to avoid stress on the extremely sensitive bare dies.

3-D integration requires a cost-effective in-process test during package assembly where the concept of known-good-die and final test before shipment does not cover the risk of cracking the stacks during the assembly of multiple dies.

Multitest's platform employs a load board that leverages the company's fabrication capabilities for fine-pitch, high-layer-count PCBs to support this 0.4mm pitch array application in a high-pin-count, multisite configuration. The final Plug & Yield solution enables highly parallel electrical in-process test of stacked die during the assembly process of 3D packages.

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