Power tip: Avoid common multilayer ceramic capacitor issues

Multi-layer ceramic (MLC) capacitors have become tremendously popular in power electronics due to their small size, low equivalent series resistance (ESR), low cost, high reliability, and high ripple current capacity. Commonly, they are used in lieu of electrolytic capacitor to enhance system performance. MLC capacitors have the advantage of a high relative permittivity material (2000-3000) compared to electrolytics with relative permittivity of 10 with the aluminum-oxide insulation of an electrolytic capacitor. The difference is important because capacitance is directly related to permittivity. On the positive side for the electrolytics, the aluminum-oxide thickness that sets the plate separation is much less than the ceramics that can result in higher capacitance density.

The permittivity of the ceramic capacitor is not stable over temperature and DC bias and needs to be understood in the design process. High permittivity ceramics are classified as Class 2. Figure 1 shows how they are grouped with a three-digit description, such as Z5U, X5R and X7R. For instance, a Z5U capacitor has a temperature rating of +10 to +85o C with a variation of +22/–56%. Even the more stable dielectrics have a sizable capacitance variation with temperature.

Things get much worse when you examine the capacitance dependence on applied bias. Figure 2 presents the bias dependence of a 22 uF, 6.3V, X5S capacitor that you typically would use as the output capacitor in a 3.3V point-of-load (POL) regulator. The capacitance drops 25 percent at 3.3V, resulting in increased output ripple and a significant impact on control loop bandwidth. If you tried to use this capacitor at 5V out, between temperature and bias, the capacitance could drop as much as 60 percent and might result in an unstable power supply due to a 2:1 increase in loop bandwidth. This is a point that ceramic capacitor vendors gloss over.

The second potential pitfall with ceramic capacitors is that they have a relatively small amount of capacitance and a low ESR. This can create problems in both the frequency and time domain. If they are used as input filter capacitors on a power supply, they can easily resonant with the input interconnect inductance and create an oscillator as we discussed in Power Tips 3 and 4. To see if you have a potential problem, estimate the parasitic interconnect inductance as 15 nH per inch and compare the filter output impedance to the power supply input resistance per the articles. A second potential problem exists in the time domain and can be experienced in systems like power-over- Ethernet (POE).