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Grasping power awareness in RTL design analysis

Posted: 08 Aug 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Common Power Format? Unified Power Format? power intent?

Another important aspect to be considered is physical placement of voltage domains in the design, where blocks/logic operating at similar voltages need to be placed near to each other. This helps to avoid congestion of power/ground nets that need to be routed based on physical placement of blocks/logic.

Power-intent aware RTL power optimization
Power intent awareness also plays a vital role in RTL power optimization. Let us consider the circuit in figure 3. In this design, we have a power management control unit (PMU), and two blocks "blk1" and "blk2". Logic transfer occurs between the switch domain (blk1) and always-on domain (blk2). In this case, data is fed from the upstream register (S) to the downstream register (D). During synthesis, isolation logic will be inserted to propagate the known logic at the switched off domain output. However, clock is still being fed to downstream register (D) which means data at the input of downstream (D) is stable due to the control signal that switches off the power domain. So, RTL power optimization tools are aware of the power intent that is defined in UPF/CPF, it can derive this stability condition and use this for gating the clock of downstream register (D), resulting in power savings.

Figure 3: Power optimization by shutting clock across domains.

Power-intent aware RTL power estimation
Power intent awareness is mandatory for early estimating power with multiple voltage islands and power islands. RTL power tools must consider switch off conditions as well as operating voltages of different islands for accurate power estimation. There is also other critical information that can be leveraged to estimate the power of additional structures that get added during implementation. RTL power estimation tools cannot only account for the additional area/leakage due to low power cells such as level shifters, isolation logic, retention cells, cells with bias capability or power switch cells, but also their impact on dynamic power.

In conclusion, we have illustrated scenarios where power intent awareness plays a critical role in verification and analysis of different aspects of the RTL design. Atrenta's SpyGlass platform provides solutions for early power intent verification at RTL, post synthesis and post layout stages and supports both the CPF and UPF formats. These solutions can be used to validate the design for not only power intent but also the impact of power management logic on CDC or DFT early at RTL to ensure successful handoff for downstream implementation.

About the author
Narayana Koduri is a senior staff applications engineer for the SpyGlass Power product line at Atrenta Inc. and has been supporting semiconductor designers in the areas of RTL power estimation, reduction and verification for the past 8 years. He has 11 years of experience in EDA and chip design. Prior to joining Atrenta, he held an application/design engineer position at Trident Tech Labs, India. Narayana holds a bachelor degree in engineering from Anna University, India.

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