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Improve SoC yields with diagnostic and repair tools for embedded memory

Posted: 09 Aug 2012 ?? ?Print Version ?Bookmark and Share

Keywords:system-on-chip? embedded memory test? 3D-ICs?

An embedded memory test solution with a comprehensive set of test algorithms that are optimized to provide out-of-box fault coverage for embedded memories in each advanced node helps improve yield ramp-up time while minimizing the required test time. The embedded test solutions developed for 90-nm technology nodes will not deliver the same level of test quality for 28-nm technology nodes, because memory defects and failure mechanisms change as process technologies shrink. The following three-step flow can be used to test algorithms covering a wide range of faults associated with advanced technology nodes:

???Memory layout to electrical circuit extraction using memory scrambling information
???Electrical circuit to fault modeling extraction using SPICE simulations. A comprehensive set of faults can be injected on electrical circuits including the memory array, address decoder, sense amplifier, and write driver to validate the coverage of test algorithms.
???Fault modeling to test algorithm extraction using test algorithm generator tools that can generate minimal March test algorithms for detection of a given set of faults.

Figure 2: Using redundant elements to improve yield of embedded memory.

Manufacturing repair
With the overall yield of an SoC being largely dependent on memory yield, it is important to implement techniques to improve it. Although the yield of native memory may be inadequate, embedded memory yield can be improved through the use of redundancy or spare elements.

In figure 2, the purple lines represent memory yield as a function of the aggregate memory bit-count in an SoC. In this example, the yield for 24 Mbit of embedded memory is close to 20% for new processes, represented by the longer purple line, assuming chip dimensions of 12 cm x 12 cm with a memory defect density of 0.8 and a logic defect density of 0.4. Through redundancy, the yield can be improved, but determining the type and quantity of redundant elements needed for a given memory requires both memory design knowledge and failure history information for the process node under consideration. Yet, simply providing the right redundant elements is not sufficient. Both the ability to detect and locate the defects in the memory and an understanding of how to allocate the redundant elements require manufacturing knowledge of defect distributions.

In order to achieve the optimized yield solution represented by the orange line in figure 2, test and repair algorithms that contain these capabilities must be utilized.

Conventional memory test algorithms detect memory failures to determine whether or not a chip is defective. For repairable memories, however, fault detection is not enough. Repairable memories need fault localization to determine which cells must be replaced. The greater the fault localization coverage, the higher the repair efficiency and therefore the obtained yield. It is very helpful to localize the exact coordinates of failed bits and associated fault classification to understand the root cause of failures.

Soft error correction
The continued scaling of complementary metal-oxide semiconductor device technologies has lead to ongoing device shrinkage and a decrease in the operating voltage of the device transistors (Vdd). Scaling has meant denser circuitry overall, thinner silicon (e.g., silicon-on-insulator) in logic applications and less charge on capacitors for volatile memory. Even low-energy alpha particles can flip a memory bit or alter timing in a logic circuit of these smaller, lower voltage chips, making them more susceptible to soft errors. In many cases, these soft errors are self-inflicted because alpha particles are commonly generated in materials adjacent to the chip, solders and in the packaging.

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