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Improve SoC yields with diagnostic and repair tools for embedded memory

Posted: 09 Aug 2012 ?? ?Print Version ?Bookmark and Share

Keywords:system-on-chip? embedded memory test? 3D-ICs?

An alternative solution to eliminate this issue is for the memory supplier to provide a description of a memory BIST engine that is implemented in the bottom logic die. In this case, the memory BIST operation is controlled from within the logic die with the stimuli and responses flowing into and out of the memory die through TSV-based interconnects. Any embedded memory test solution used with 3D-IC chips requires complete test, repair and diagnostics support for various external memory types, such as SRAM, DRAM, DDR2, DDR3, LPDDR2, and external memory interfaces such as DDR PHY and Wide I/O memory that might be implemented on the chip, in order to test the external memories and TSV interconnects.

Process improvement
Many embedded memory test algorithms are targeted at catching random defects. However, as a result of shrinking geometries and the introduction of new material in the fabrication process, systematic defects now have a significant impact on process yield, necessitating the implementation of other methods to address manufacturing defects in embedded memories.

Adequate diagnosis and failure analysis is necessary to discover the root causes of the yield-limiting factors and accordingly update the manufacturing process. To expedite diagnostics, the embedded memory test solution needs to rapidly, cost-effectively, and accurately identify, analyze, isolate, and classify memory faults as designs are readied for transition from first silicon to volume manufacturing. A solution with automatic test vector generation, fault analysis, and root-cause failure guidance based on silicon test results would enable test and product engineers to rapidly analyze failures manifested in embedded memories and inspect the physical location and class of each fault to determine the root cause.

Improving time-to-volume
SoC complexity is increasing as are time-to-market pressures, forcing SoC providers to find ways to get to volume production faster. Time-to-volume (TTV) consists of SoC design time and production ramp-up time. Reducing SoC design time is not a recent discussion. Reusing pre-designed cores and ensuring ease of integration is a viable way to address the growing SoC design gap and it is common for SoC designers to obtain embedded memories from IP providers.

Traditionally, yield optimization is done during the ramp-up period following the design stage. However, because of tight time-to-market windows, the ramp-up period of an SoC may start before the traditional defect densities and corresponding yield maturity levels are achieved, which results in a longer ramp-up time. Yet it is possible to reduce the ramp-up period, and therefore TTV, if the yield optimization effort starts before the ramp-up period. For embedded memories this can be done if a memory IP provider conducts yield optimization during the IP design and characterization phases before SoC ramp up by:

???Fabricating memory IP test chips, characterizing them and applying knowledge from the fabrication process to improve the yield of the memory IP block, which will result in silicon-proven memory IP before the SoC production ramp up starts.
???Designing all necessary memory repair functions into the memory IP and the SoC in advance, which augments the volume of fault-free SoCs and simplifies the ramp-up effort.
???Designing all necessary diagnosis and failure analysis functions into the memory IP, which will be the basis of the process improvement that will be performed during the ramp-up period.
Today's embedded memories require solutions capable of addressing yield and reliability needs such as fault detection, repair at the manufacturing level, diagnosis for process improvement and field repair capabilities, all with minimal impact on the functional design. In addition, they must be able to address the test, repair and diagnostics requirements of emerging technologies such as 3D-ICs, which bring with them new types of defects. At the same time, these solutions need to minimize the manufacturing cost and reduce TTV. For example, Synopsys' DesignWare STAR Memory System aims to be a comprehensive solution for embedded memory test, repair and diagnostics to optimize SoC yield, while staying within cost and schedule parameters.

References
[1] Zorian, Y., "Embedded Memory Test & Repair: Infrastructure IP for SoC Yield", IEEE International Test Conference (ITC), pp. 340-349, 2002
[2] Marinissen, E.J., Zorian, Y., "Testing 3D Chips Containing Through-Silicon Vias", IEEE International Test Conference (ITC), 2009
[3] Shoukourian S. K., Vardanian V. A., Zorian Y., "A Methodology for Design and Evaluation of Redundancy Allocation Algorithms", VLSI Test Symposium, 2004, pp. 249-260.
[4] Zorian Y., Shoukourian S. K., "Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield", IEEE Design & Test of Computers 20(3), 2003, pp. 58-66.
[5] Zorian Y., "Embedding Infrastructure IP for SOC Yield Improvement:, Design Automation Conference, 2002, pp. 709-712

About the authors
Sandeep Kaushik is the Sr. Product Marketing Manager for the embedded memory test and repair products at Synopsys. Sandeep brings over 12 years of experience in the field of Design-for-Test. He holds a Bachelor's Degree in Electrical Engineering from the Indian Institute of Technology in Delhi, India and a Master's Degree in Electrical Engineering from Stanford University. He is currently working toward his Master's Degree in Business Administration from the Haas School of Business, University of California, Berkeley.

Dr. Yervant Zorian is the Chief Architect at Synopsys for embedded test & repair products.Formerly, he was Distinguished Member of Technical Staff AT&T Bell Laboratories, Vice President and Chief Scientist of Virage Logic and Chief Technologist at LogicVision. He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania. He is currently the President of IEEE Test Technology Technical Council (TTTC), the Vice General Chair of Design Automation Conference (DAC), the Editor-in-Chief Emeritus of Design & Test of Computers, the founder & chair of IEEE 1500 Standardization Working Group, and an Adjunct Professor at University of British Columbia.

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