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The significance of JESD204

Posted: 14 Aug 2012 ?? ?Print Version ?Bookmark and Share

Keywords:analog to digital converters? DACs? FPGA?

A new converter interface is steadily picking up steam and appears to become the protocol of choice for future converters. This new interface, JESD204, was originally rolled out several years ago, but has undergone revisions that are making it a much more attractive and efficient converter interface. As the resolution and speed of converters has increased, the demand for a more efficient interface has grown.

The JESD204 interface brings this efficiency and offers several advantages over its CMOS and LVDS predecessors in terms of speed, size, and cost. Designs employing JESD204 enjoy the benefits of a faster interface to keep pace with the faster sampling rates of converters. In addition, there is a reduction in pin count which leads to smaller package sizes and a lower number of trace routes that make board designs much easier and offers lower overall system cost. The standard is also easily scalable so it can be adapted to meet future needs. This has already been exhibited by the two revisions that the standard has undergone. The JESD204 standard has seen two revisions since its introduction in 2006 and is now at revision B.

As the standard has been adopted by an increasing number of converter vendors and users as well as FPGA manufacturers, it has been refined and new features have been added that have increased efficiency and ease of implementation. The standard applies to both analog to digital converters (ADCs) as well as digital to analog converters (DACs) and is primarily intended as a common interface to FPGAs (but may also be used with ASICs).

JESD204: What is it?
In April of 2006 the original version of JESD204 was released. The standard describes a multigigabit serial data link between converter(s) and a receiver, commonly a device such as an FPGA or ASIC. In this original version of JESD204, the serial data link was defined for a single serial lane between a converter or multiple converters and a receiver. A graphical representation is provided in figure 1. The lane shown is the physical interface between M number of converters and the receiver which consists of a differential pair of interconnect utilizing current mode logic (CML) drivers and receivers. The link shown is the serialized data link that is established between the converter(s) and the receiver. The frame clock is routed to both the converter(s) and the receiver and provides the clock for the JESD204 link between the devices.

Figure 1: JESD204 original standard.

The lane data rate is defined between 312.5 Megabits per second (Mbps) and 3.125 Gigabits per second (Gbps) with both source and load impedance defined as 100 ? 20%. The differential voltage level is defined as being nominally 800 mV peak-to-peak with a common mode voltage level range from 0.72 V to 1.23 V. The link utilizes 8b/10b encoding which incorporates an embedded clock, removing the necessity for routing an additional clock line and the associated complexity of aligning an additional clock signal with the transmitted data a high data rates. It became obvious as the JESD204 standard began being used that the standard needed to be revised to incorporate support for multiple aligned serial lanes with multiple converters to accommodate increasing speeds and resolutions of converters.

Figure 2: First Revision C JESD204A.

This realization led to the first revision of the JESD204 standard in April of 2008 which became known as JESD204A. This revision of the standard added the ability to support multiple aligned serial lanes with multiple converters. The lane data rates, supporting from 312.5Mbit/s up to 3.125Gbit/s remained unchanged as did the frame clock and the electrical interface specifications. Increasing the capabilities of the standard to support multiple aligned serial lanes made it possible for converters with high sample rates and high resolutions to meet the maximum supported data rate of 3.125Gbit/s. Figure 2 shows a graphical representation of the additional capabilities added in the JESD204A revision to support multiple lanes.

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