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The significance of JESD204

Posted: 14 Aug 2012 ?? ?Print Version ?Bookmark and Share

Keywords:analog to digital converters? DACs? FPGA?

To allow for more flexibility, the JESD204B revision transitions from the frame clock to the device clock. Previously, in the JESD204 and JESD204A revisions, the frame clock was the absolute timing reference in the JESD204 system. Typically, the frame clock and the sampling clock of the converter(s) were usually the same. This did not offer a lot of flexibility and could cause undesired complexity in system design when attempting to route this same signal to multiple devices and account for any skew between the different routing paths. In JESD204B, the device clock is the timing reference for each element in the JESD204 system. Each converter and receiver receives their respective device clock from a clock generator circuit which is responsible for generating all device clocks from a common source. This allows for more flexibility in the system design, but it requires that the relationship between the frame clock and device clock be specified for a given device.

Why should we pay attention to it?
In much the same way as LVDS began overtaking CMOS as the technology of choice for the converter digital interface several years ago, JESD204 is poised to tread a similar path in the next few years. While CMOS technology is still hanging around today, it is mostly been overtaken by LVDS. The speed and resolution of converters as well as the desire for lower power eventually renders CMOS and LVDS inadequate for converters. As the data rate increases on the CMOS outputs, the transient currents also increase and result in higher power consumption. While the current, and thus power consumption, remains relatively flat for LVDS, the interface has an upper speed bound that it can support. This is due to the driver architecture as well as the numerous data lines that must all be synchronized to a data clock. Figure 4 illustrates the different power consumption requirements of CMOS, LVDS, and CML outputs for a dual 14bit ADC.

Figure 4: CMOS, LVDS, and CML driver power comparison.

At approximately 150 C 200 MSPS and 14 bits of resolution, CML output drivers start to become more efficient in terms of power consumption. CML offers the advantage of requiring fewer output pairs per a given resolution than LVDS and CMOS drivers due to the serialization of the data. The CML drivers specified for the JESD204B interface have an additional advantage since the specification calls for reduced peak to peak voltage levels as the sample rate increases and pushes up the output line rate. The number of pins required for the same give converter resolution and sample rate is also considerably less. The table gives an illustration of the pin counts for the three different interfaces using a 200 MSPS converter with various channel counts and bit resolutions. The data assumes a synchronization clock for each channel's data in the case of the CMOS and LVDS outputs and a maximum data rate of 4.0Gbit/s for JESD204B data transfer using the CML outputs. The reasons for the progression to JESD204B using CML drivers become obvious when looking at this table and observing the dramatic reduction in pin count that can be achieved.

Table: Pin count comparison C 200 MSPS ADC.

We have seen the trend that is pushing the converter digital interface toward the JESD204 interface defined by JEDEC. Our company has been involved with the standard from the beginning when the first JESD204 specification was released. To date, Analog Devices has released to production several converters with the JESD204 and JESD204A compatible outputs and is currently developing products with outputs that are compatible with JESD204B.

As the speed and resolution of converters have increased, the demand for a more efficient digital interface has increased as well. The industry began realizing this with the JESD204 serialized data interface. The interface specification has continued to evolve to offer a better and faster way to transmit data between converters and FPGAs (or ASICs). The interface has undergone two revisions to improve upon its implementation and meet the increasing demands brought on by higher speeds and higher resolution converters. Looking to the future of converter digital interfaces, it is clear that JESD204 is poised to become the industry choice for the digital interface to converters. Each revision has answered the demands for improvements on its implementation and has allowed the standard to evolve to meet new requirements brought on by changes in converter technology. As system designs become more complex and converter performance pushes higher, the JESD204 standard should be able to adapt and evolve to continue to meet the new design requirements necessary.

About the author
Jonathan Harris is a product applications engineer, High-Speed Converter Group, Analog Devices Inc. (Greensboro, NC). He has over 7 years of experience as an applications engineer supporting products in the RF industry. Jonathan received his MSEE from Auburn University and his BSEE from UNC-Charlotte.

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