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Optimize dynamic power signature of digital ICs to reduce power noise

Posted: 15 Aug 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Power noise integrity? dynamic voltage? scaling technology nodes?

Power noise integrity (PNI) is becoming the topmost IC design focus, as product quality, circuit reliability and lifetime robustness are increasingly important parameters of strategic business value in high-volume IC products. All the while, higher levels of SoC integration, advanced low-power design techniques, increasing power density and faster circuit switching at scaling process nodes are causing critical PNI challenges at 28 nm and beyond. Power Delivery Network (PDN) design is an increasingly complicated task, and key to semiconductor business success.

At the technical level, flip-chip packages, on-chip voltage regulators, fine granularity power gating, extensive clock gating, together with lower supply voltages leading to lower power noise margins, and decreasing effectiveness of on-chip decoupling capacitors (decaps) in scaling geometries, cause mounting challenges to PDN designers. The need to control the adverse effects of power noise in digital circuits is adamant. Transient poweroften simply referred to as dynamic power, not to be confused with switching power C is the direct cause of dynamic voltage drop and power noise problems. Depending on when and where it happens, dynamic voltage drop impacts circuit timing in a number of different ways. It may cause both setup- and hold-time violations, and may even cause bit errors in signal paths as well as on-chip RAMs. Additionally, the precise effect of digital power noise on the performance of analog blocks in mixed-signal designs is very difficult to determine.

Most commonly used methods to ensure PNI are focused on physical-level aspects of PDN implementation: ensuring the construction of a system to provide proper delivery of the power required. At the chip-level, this means adding enough metal and enough decaps to accommodate the transient current demand of the cells. But in this there are conflicting design objectives. In order to reduce the resistive drop in the metal, wide straps are warranted. But this reduces the metal available for signal routing. Using too much metal resources may thus lead to routing congestion and ultimately lower area utilization. In order to reduce the dynamic voltage drop, many decaps are warranted. But more decaps increases the leakage power. If there is not enough white space available for decaps, the chip area also increases. Furthermore, power gating is becoming widespread and implemented at ever finer granularity [1]. In order to limit resistive voltage drop across power gates, it is necessary to keep dynamic current peaks through the power gates to a minimum. This can be achieved by adding decaps locally. But in power gated architectures, excessive use of decaps results in increased rush-currents when bringing up sleeping power regions, causing further challenges to dynamic power integrity and slow wake-up time. Worse yet, increasing capacitance and decreasing resistance is, in general, a direct path to LC-instability, which may cause resonant ringing effects in the chip-package-board PDN system. This is of particular concern in flip-chip packages in which C4 bumps offer a low impedance path between the chip and the package and board. Since the board, or even the package, may not be known at the time of designing the chip, keeping R high is the safe choice with regards to resonance stability. This may obviously be counter-productive when trying to minimize on-chip dynamic voltage drop though. Clock-gating is another low-power technique which, while constituting an effective approach to bringing down functional mode power, can cause PNI problems. Switching large sections of the clock network on or off may lead to significant cycle-to-cycle jitter and result in both setup- and hold-timing violation scenarios that are very hard, if not impossible, to predict or model. Also, clock-gating results in a discrepancy in power in different modes of operation, and the PDN must be designed for the worst-case across all modes. In test-mode everything is on, so do you implement the PDN for this power-wise worst-case scenario, or do you accept prolonged test time?

In summary, PNI challenges are mounting as the industry moves to the 28 nm process node and beyond, and as SoC design size and architectural power-complexity increases.

Complementary to physical PDN implementation approaches, there is another way to ensure PNI: optimizing the dynamic power signature of a digital circuit will increase the effectiveness and robustness of any given PDN implementation, simply because the dynamic strain on the system will be less. Deliberate power shaping is the process of shaping the dynamic current demand waveform, the power noise profile, of a circuit. Teklatech provides an extensive Dynamic Power Shapingsolution for digital IC design in its FloorDirector tool.

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