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ARM, Cadence link POPs to digital design software

Posted: 13 Aug 2012 ?? ?Print Version ?Bookmark and Share

Keywords:processor optimization packages? Encounter? SoCs?

ARM Holdings plc and EDA software vendor Cadence Design Systems Inc. have collaborated together to link ARM's processor optimization packages (POPs) to Cadence's Encounter, a software for digital design.

The combined efforts of ARM and Cadence have produced further improvements in performance and power consumption tradeoffs for system-chips (SoCs) based on Cortex A-series processor cores. Details regarding the design quality achieved with POPs when linked to design tools from other EDA vendors are still sketchy.

ARM, which licenses processor architectures and core designs at the logical level, have also provided a physical IP that can be used to construct the transistor detail of processors on particular CMOS manufacturing processes. However, with such design details becoming time consuming, ARM has begun providing processor optimization packages that provide the detailed design and allow options for developers to move away from the reference and make changes. With most of the work already done, design has picked up its pace and time to market has also been improved.

However, for system-on-chip designs the processor and its optimization have to be considered in the SoC context.

Cadence and ARM have come up with an initial approach for the Cortex-A9 processor on the 40LP 40-nm manufacturing process technology, including low threshold voltage, from foundry Taiwan Semiconductor Manufacturing Co. Ltd. The collaboration is being extended to the 28HPM process form TSMC and to include single, dual and quad-core implementations of Cortex-A9 and Cortex-A15 processors.

John Heinlein, vice president of marketing for the physical IP division at ARM, has stated that the work between Cadence and ARM provides higher performance at a lower power than previously available.

- Peter Clarke
??EE Times





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