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Initial draft of 3-D DRAM specs released to HMCC members

Posted: 16 Aug 2012 ?? ?Print Version ?Bookmark and Share

Keywords:3-D DRAM memory stack? PHY? aggregate bi-directional bandwidth?

An initial draft of interface specifications for a 3-D DRAM memory stack has been release to its members by the Hybrid Memory Cube Consortium (HMCC). A final review of the spec is currently in progress and the plans will be publically release near the end of the year.

The group is led by Micron and Samsung. Other members include Altera, ARM, Hewlett-Packard, IBM, Microsoft, Open-Silicon, SK Hynix and Xilinx.

The group has so far defined two specificationsan interface protocol and a short-reach physical layer channel. The PHY is optimized for use connecting a memory cube and chips sitting multiple inches of printed circuit board traces away in a networking system.

The they will also define an ultra-short reach PHY. It aims to extend less than three inches and is optimized to connect the cube with die, probably on a single multichip module.

At the moment, only members have access to the initial drafts and provide input on them. Once the review process is complete, the drafts will be available to the public. The group is still open to accepting new members.

The spec is primarily targeted at high-performance networking, industrial, and test and measurement applications. IBM has also suggested it will use the cubes for high-end servers. The cubes contain both DRAM memory chips and a memory controller.

Micron has stated that it will deliver 2 and 4GB versions of the cubes in early 2013, providing aggregate bi-directional bandwidth of up to 160GB/second.

Separately, the Jedec standards group is working on a follow on to the 12.8 Gbit/second Wide I/O interface that targets mobile applications processors. The so-called HB-DRAM or HBM effort is said to target a 120-128GB/second interface and is led by the Jedec JC-42 committee including representatives from Hynix and other companies.

- Rick Merritt
??EE Times

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