Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > FPGAs/PLDs

Guide to configuring FPGAs over USB

Posted: 06 Sep 2012 ?? ?Print Version ?Bookmark and Share

Keywords:FPGAs? JTAG? SRAM?

For the past few decades, engineers have been striving to decrease the size of electronic systems as well as increase flexibility. With the advent of reprogrammable FPGAs, systems could be made that were less expensive and could be upgraded on the fly. This article discusses on how to configure FPGA-based systems over USB to implement the flexibility of in-field upgrades. This method can also serve to replace the popular JTAG configuration interface and eliminate the need for a separate JTAG connector on the board, hence reducing cost and board space.

Field programmable gate arrays (FPGA) are simple programmable logic blocks with a massive fabric of electrically programmable interconnects between the logic blocks. An FPGA enables users to configure the logic blocks and the interconnections between the logic blocks. FPGAs were introduced to implement the entire functionality of a system on one chip and provide flexibility of reprogramming. Today, FPGAs cover a broad market of applications such as automotive, industrial, medical, consumer electronics networking, security, high performance computing, video and imaging, digital signal processing, etc. We will see the various types of FPGA configuration in the below sections.

FPGA configuration
FPGAs work in two modes: configuration mode and user mode. On power up, the FPGA enters the configuration mode for programming. Configuring a FPGA means sending a bit stream of '0' and '1' into the device through special pins. Once the FPGA is configured, it switches into user mode to perform the programmed logic function.

Most FPGAs use SRAM to store configuration data. Since SRAM is a volatile configuration, the configuration data needs to be downloaded to the SRAM upon power up. These configurations can also be automatically loaded from non-volatile memories like PROM, SPI Flash, or an external processor chip. Microprocessors, microcontrollers and digital signal processors can also download the configuration data to the FPGA's SRAM. Apart from these methods, the configuration can be also be downloaded via the most popular JTAG interfaces, USB interfaces, etc.

Types of FPGA configuration
Configuration of an FPGA can be performed by either placing the FPGA in master mode or slave mode. In Master mode, the FPGA generates the configuration clock and controls the configuration data. In this mode, the FPGA generally downloads the configuration bit stream from non-volatile memories like SPI, Flash, and PROM. When using a SPI Flash, the FPGA acts as a SPI master where the configuration is downloaded from this SPI Flash as shown in figure 1A. In figure 1B and figure 1C, the FPGA downloads the configuration data from PROM. Although non-volatile memory like PROM can be internal or external, it is usually external to the FPGA.

In this slave mode, the FPGA can be configured using external intelligent devices like microcontrollers, microprocessors, digital signal processors, etc. or using a JTAG or USB interface.

The three most commonly used methods smart devices like microcontroller, microprocessor, and DSPs use to load configuration data are synchronous serial, SPI slave, and parallel modes.

Synchronous serial interface

Usually two lines C data and clock C are used to download the configuration in this method. On the rising-edge of the configuration clock, the configuration data bits are shifted into the FPGA.

SPI slave mode

1???2?Next Page?Last Page

Article Comments - Guide to configuring FPGAs over USB
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top