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40G/100G Ethernet IP aimed at networking IC dev't

Posted: 04 Sep 2012 ?? ?Print Version ?Bookmark and Share

Keywords:40G/100G Ethernet IP? networking application? media access controller? Hybrid Memory Cube? DDR3?

Open-Silicon Inc., together with CoMira Solutions, has uncloaked a 40G/100G Ethernet media access controller (MAC) IP and 40G/100G physical coding sublayer (PCS) IP.�When combined with Open-Silicon's Interlaken, Hybrid Memory Cube (HMC) or DDR3 controllers, the IEEE 802.3ba-compliant Ethernet IP offers a complete IP solution for networking applications, added the firms.

For the two cores, the design and verification process includes FPGA emulation, documentation review, UNH compliance testing, and comprehensive timing and functional verification. For qualification, prior to release all Open-Silicon IP cores go through Open-Silicon's IP qualification process, which has been developed and continually enhanced through the successful integration of more than 900 IP cores, boasted the companies.

"Our customers have been asking for high quality leading edge Ethernet IP for their next generation products, including Ethernet 40G/100G MACs," said Steve Erickson, VP and GM IP and platform development, Open-Silicon.

"Today's chip designers and suppliers face significant challenges integrating an increasingly disparate collection of third-party IP," said Qasim Shami, president and CEO of CoMira Solutions. "By co-developing our IP with Open-Silicon, our customers will benefit from a more tightly-coupled IP and silicon development platform, enabling a higher degree of predictability and faster time to market."

The 40G/100G MAC and PCS are highly modular enabling system level solutions from 10G to 100G, and are ideal for low-latency applications such as data center switches where higher performance is required. The small footprint implementation leads to lower gate counts and smaller die sizes, which allow for an efficient design in high-port count devices. Built on a highly configurable architecture supporting a number of different SerDes configurations and user interface options, the 40G/100G MAC and PCS IP cores can be quickly tuned to meet user requirements. Comprehensive system-level verification and automated infrastructure, including a web-based IP builder, allows for quick tradeoff analysis and system-level integration.

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