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IBM, STM to create NEMS-based logic process

Posted: 05 Sep 2012 ?? ?Print Version ?Bookmark and Share

Keywords:nanometer-scale relays? CMOS transistor logic? digital logic designs?

Backed by the European Commission, IBM and STMicroelectronics have teamed up to develop a logic process based on nanometer-scale relays that remain compatible with conventional CMOS transistor logic. Such a system will significantly decrease leakage current thereby resulting in lower off-state power depletion. The European arm of IBM Research, based in Zurich, Switzerland, will lead the Nano-Electro-Mechanical Integration And Computation (NEMIAC) project.

Alongside IBM and STMicroelectronics are academic researchers from the Ecole Polytechnique Federale de Lausanne, Kungliga Tekniska Hoegskolan and the universities of Bristol and Lancaster.

The three-year collaborative research project has a budget of about $5 million, of which the European Commission is providing roughly $3.1 million.

The motivation for the research is that as transistors have been miniaturized leakage power consumption is becoming as large as active power consumption and this is a particular issue for emerging applications such as autonomous sensors nodes, wireless communications and mobile computing.

The NEMIAC project aims to produce a process based on what it calls nano-electromechanical (NEMS) switches suitable for embedded systems and offering 3-D integration with CMOS. The researchers are being asked to show a magnitude improvement in energy efficiency with no performance penalty compared with solid-state. The process is also expected to have higher radiation resistance and higher temperature operation than CMOS.

The relays are expected to have a footprint of less than 3-micron by 3-micron and demonstrate a switching time of the order of 10 nanoseconds. Proving the reliability under billions of switching operations will be an important task prior to commercial deployment.

The project is expected to produce a number of digital logic designs as proof of the process and innovative circuit architectures for low-power applications. In parallel design and simulation methodologies are going to be developed to aid exploration of the design-space and demonstrate the feasibility of a small microprocessor.

- Peter Clarke
??EE Times

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