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EVE's ZeBu, SystemVerilog used by Fujitsu Kyusyu Network

Posted: 05 Sep 2012 ?? ?Print Version ?Bookmark and Share

Keywords:ZeBu? SystemVerilog? UVM co-emulation?

EVE, a hardware/software co-verification firm, has revealed that its ZeBu hardware-assisted verification platform and SystemVerilog methodology have been adopted by Fujitsu Kyusyu Network Technologies Ltd. The Japanese company implemented an acceleration flow of its Universal Verification Methodology (UVM) testbench with the ZeBu emulator.

"Recently, the gate size of an LSI/FPGA has grown larger and larger, and the functionality has gotten more complicated," said Eisuke Yuri, professional engineer, Fujitsu Kyusyu Network Technologies. "In particular, during the verification phase, the increase in the number of test scenarios and the simulation time become critical. UVM, a new verification methodology, is getting popular to overcome these situations. Accordingly, we have focused on a UVM co-emulation technology that executes the UVM testbench on an HDL simulator and the Design Under Test (DUT) is mapped to ZeBu.

"Due to UVM's object oriented programming (OOP), the UVM testbench that we developed for HDL simulation could be easily integrated with ZeBu with minimal change to the driver class, the monitor class and the test class. The co-emulation environment provided remarkable simulation acceleration as ZeBu's transaction technology minimized the communication overhead between the testbench and the emulator."

"We are delighted to see a successful deployment of ZeBu in a real UVM test environment," stated Luc Burgun, EVE's CEO and president. "The results reported by Fujitsu Kyusyu Network Technologies are proof of the value of the ZeBu emulation platform and our SystemVerilog technology."





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