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Incorporating flexibility to 32bit MCU designs

Posted: 20 Sep 2012 ?? ?Print Version ?Bookmark and Share

Keywords:microcontroller? analogue-to-digital converters? DACs?

Nowadays, 32bit microcontroller (MCU) designs integrate a broad variety of standard peripherals, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), universal synchronous/asynchronous transmitters (USARTs) and timers.

While this peripheral integration is intended to address a wide range of general-purpose applications, embedded developers commonly consider these on-chip peripherals to be "check box" items, and the implementation of this peripheral integration usually ends up providing limited value.

In addition, the lack of smart interconnectivity among peripherals often forces designers to add significant amounts of glue logic to ensure proper use of the MCU's features, resulting in unnecessary incremental development costs and system complexity.

Standard MCU peripherals are intended to support a broad range of general-purpose embedded applications. However, peripherals often are integrated into 32bit MCU designs with little or no thought about how they can enable a more cost-effective or simpler application implementation.

Let's take a closer look at implementations of standard MCU peripherals that provide system-level value and application benefits that help designers get the most out of every feature in the MCU while simultaneously reducing the bill of materials (BOM) and simplifying the embedded design.

Innovative implementations of standard MCU peripherals, such as I/O with deterministic pulse generation and level shifters, USART input noise-filtering for reliable communications, capacitive-sense tamper detection systems, current-based communication using interconnecting digital-to-analogue converters (IDACs) and synchronous current-to-voltage converter systems, can provide significant value for 32bit embedded designs.

I/O with deterministic pulse generation and level shifters
Some 32bit applications require the generation of one or more pulses with precisely-controlled pulse widths.

Examples include a trigger for an external event or a test pulse to stimulate an external device within a specific time window. A typical software-implemented I/O toggle cannot guarantee the pulse width since the software is subject to interruptions and latencies, and using a timer consumes a valuable and typically pin-constrained resource.

An innovative solution to this design challenge implements pulse generation at the I/O level (figure 1). This system provides the capability to set the initial and final value of the I/O in one 32bit register (allowing the initial and final value to be set in a single 32bit word write) along with a mask register to enable multiple pins at any time and a programmable 5bit delay time.

Figure 1: Pulse generation register implementation.

Once initiated, the pulse generator waits for a number of peripheral clock cycles set by the delay time before driving the pre-programmed final value onto the I/O pin, enabling simple yet effective deterministic pulse generation. Figure 1 shows a practical implementation of this feature at the register level.

3 V-to-5 V level shifting
Another common challenge in factory automation and industrial control applications is interfacing with legacy 5 V I/O systems. While a 5 V-tolerant I/O provides a means of receiving input from 5 V outputs, bidirectional communication requires the capability to drive 5 V logic levels. To address this problem, system designers are often forced to add external glue logic, such as external level shifters, increasing PCB layout complexity and BOM cost.

An integrated, versatile level shifting system can be achieved by enabling a 3 V I/O and a 5 V drive I/O that are directly interconnected on the same device, thus enabling a 3 to 5 V level shifting capability. This connectivity enables the developer to connect any output peripheral that does not already go to the 5 V drivers through an external wire that can be converted to a 5 V driver.

Figure 2 provides an example in which a timer output that is typically in a 3 V domain can be level shifted by externally connecting the timer output to one input of the 3 V I/Os that are internally connected with the 5 V drive. The output of the corresponding 5 V drive output provides a 5 V timer output.

Figure 2: Internal level shifter system.

Current-based communications using IDACs
Applications developed to support noisy environments, such as factory floors, face the major challenge of providing reliable communications in the presence of high noise levels. Typical communications interfaces, such as USART, SPI and I2C, have proven to offer some level of reliability. However, these applications are always pushed to their limits. One solution is to implement current-based communications using IDACs to enable communications protocols with high levels of noise immunity.

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