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ReRAM in 28nm logic process piques TSMC's interest

Posted: 28 Sep 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Resistive RAM? CRRAM? MOSFET? non-volatile memory? CMOS logic process?

The innovation of embedding Resistive RAM (ReRAM) into mainstream logic process technology has caught the eye of Taiwan Semiconductor Manufacturing Co.

During the 2012 International Electron Devices Meeting, a paper authored by a research team from National Tsing-Hua University, which is affiliated with TSMC, stated that a contact RRAM (CRRAM) cell has been realised in a HKMG 28-nm CMOS logic process without the use of any additional masking or process steps. The paper, entitled "High-K metal gate contact RRAM (CRRAM) in pure 28-nm CMOS logic process", stated that the process was done using a 35nm by 35nm contact hole.

Although no additional information was released in advance of the conference, online searches revealed that the Tsing-Hua research team has previously worked with titanium-oxide based ReRAMs, typically in a TiN/TiON/SiO2 stacked arrangement sitting at the base of a tungsten contact plug attached to the drain of a conventional planar MOSFET.

The design is said to be particularly compact compared with other types of ReRAM arrays and compatible with conventional logic manufacturing processes. As recently as 2010, the team was working on a 1T-plus-1R ReRAM in 90-nm CMOS logic and claiming 1 million read-write cycle endurance.

The amount of memory included on system chips is growing and becoming increasingly responsible for much of the power consumption. The facility to hold data in dense non-volatile memory on a SoCrather than in power consuming SRAM for even a few processor cyclescould drive power savings in leading-edge manufacturing.

The fact that the CRRAM can be implemented without any addition to the processing deck indicates a potentially easy introduction into chip manufacturing. However the fact that the IEDM paper is still essentially academic and written at the memory-cell level rather than at the array level indicates that more R&D is to be done. A demonstration or projection of considerably higher endurance would also be desirable.

The paper also suggests a topic to watch for at another key chip gathering, the International Solid States Circuits Conference in February.

- Peter Clarke
??EE Times

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