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TSMC releases 20nm, CoWoS design reference

Posted: 11 Oct 2012 ?? ?Print Version ?Bookmark and Share

Keywords:CoWoS Reference Flow? design infrastructure? 3D IC? integrated passive device?

TSMC has unveiled its 20nm and Chip on Wafer on Substrate (CoWoS) design support within the Open Innovation Platform (OIP). The Reference Flow enables double patterning technology (DPT) design using proven design flows. In addition, TSMS stated that EDA vendors' tools are qualified to work with TSMC 20nm process technology by incorporating DPT aware place and route, timing, physical verification and design for manufacturing (DFM).

The silicon-validated CoWoS Reference Flow enables multi-die integration to support high bandwidth, low power and can achieve fast time-to-market for 3D IC designs, said the company. The CoWoS flow also benefits designers by allowing them to use existing, mainstream tools from EDA vendors.

TSMC's 20nm Reference Flow enables 20nm design with DPT aware capabilities to reduce design complexity and deliver required accuracy. DPT enablement includes pre-colouring capability, new RC extraction methodology, DPT sign-off, physical verification and DFM. In addition, TSMC and its ecosystem partners design 20nm IP for DPT compliance to accelerate 20nm process adoption.

The CoWoS Reference Flow enables 3D IC multi-die integration. The CoWoS Reference Flow allows a smooth transition to 3D IC with minimal changes in existing methodologies. It includes the management of placement and routing of bumps, pads, interconnections and C4 bumps; innovative combo-bump structure; accurate extraction and signal integrity analysis of high-speed interconnects between dies; thermal analysis from chip to package to system; and an integrated 3D testing methodology for die-level and stacking-level tests.

The Custom Design Reference Flow enables DPT in 20nm custom layouts. It provides solutions to 20nm process requirements, including a direct link with simulators for the verification of voltage-dependent DRC rules, and integrated LDE solutions and handling of HKMG technology. RF Reference Design Kit provides new high frequency design guidelines, TSMC said. These consist of 60GHz RF model support, high performance electromagnetic (EM) characterisation that enables customer design capability through the examples of 60GHz front-to-back implementation flow and integrated passive device (IPD) support.





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