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Verification debugger cuts op'n time by 40%

Posted: 11 Oct 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Incisive Debug Analyser? hardware verification language? hardware description language?

Cadence Design Systems Inc. has announced a verification debug product for RTL, testbench and SoC verification that according to the company offers significant reductions in debug time and effort. The company added that Cadence customers who have used the Incisive Debug Analyser have reported average time savings of up to 40 per cent or more.

The Incisive Debug Analyser allows users to step forward or backward through their hardware verification language (HVL) and hardware description language (HDL). Additionally, users can click directly on a line or variable to jump forward or backward through time to the point when the source code line was executed or a variable value changed, allowing them to pinpoint the bug(s), indicated Cadence.

Other unique features include integrated, interactive log file analysis capabilities with smart filtering and clickable messages that take users directly to the point of interest in either the source code or the waveform database. The debugger provides relevant debug investigation information that allows users to quickly and easily filter messages coming from any platform (HVL and HDL code) and explore the cause of the messages by providing causality relations and debugging leads.

The Incisive Debug Analyser integrates seamlessly into existing Incisive debug flows, fully leveraging SimVision for waveform and transaction-level debug. It is scheduled for release by year's end.

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