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Memory/Storage??

Exploring split-gate thin-film storage

Posted: 17 Oct 2012 ?? ?Print Version ?Bookmark and Share

Keywords:split-gate thin-film storage? NVM? ferroelectric RAM?

Within the category of flash memory, there are two major architectures: NOR and NAND. NOR flash architecture connects all of the bits along a column of the memory array in parallel, similar to the pull-down portion of a NOR logic gate. NOR flash provides the best read and write performance, but each bit typically requires a dedicated contact to the bitline, thus limiting how small the bit can be made.

NAND flash architecture involves wiring a string of bits within the memory array in series, similar to the pull-down portion of a NAND logic gate. This eliminates the need for dedicated contacts in each bit and allows NAND to achieve the lowest area (and thus cost) per bit, with some compromises in read and write performance, operating range, and robustness.

Another way to divide the usage of flash memory is to distinguish between discrete flash (external to the chip containing the processor) and embedded flash (in which the flash is 'embedded' on the same piece of silicon as the processor). Discrete flash is used where a large amount of flash memory (say 32 MB or more) is needed at a low overall system cost, while embedded flash is used when a more moderate amount of flash memory (8 KB to 8 MB, perhaps 16 MB in future systems) is needed, and where the unique advantages gained by embedding the flash are desired. These advantages include lower latency and higher bandwidth for executing code out of the flash memory, reduced power consumption, reduced electromagnetic emissions, enhanced security of code and data, and optimization of the flash design to meet a specific product's application.

Because NOR flash matches the requirements of embedded flash applications (moderate byte count but enhanced performance, operating range and robustness), NOR architectures are almost always used in embedded flash applications.

What is SG-TFS?
Further confining our scope to the use of embedded NOR flash onboard many of today's microcontrollers, smartcards and digital signal processors, the most common bit cell types are the one-transistor floating-gate (1T-FG) cell and the 1.5-T, or split-gate cell. 1T-FG cells are similar to those used in most discrete NOR flash products, and they play a very important role in embedded NVM applications, because they typically provide the smallest cell size, and are proven for rigorous automotive applications. However, 1T-FG cells require a relatively large chip area to contain the overhead needed for each sector, and they often require fairly large currents to program.

In contrast, split-gate cells often involve larger bit cell sizes, but they can be programmed with about 10% of the current used for typical 1T-FG cells, and the overhead associated with each sector is reduced. This has made split-gate cells a popular choice for embedded flash, particularly where the total byte count is lower and where it is desired to have many small erasable sectors, rather than a few large sectors. Because the read operation of a split gate cell usually involves lower-voltage transistors, it can also be accessed with faster read access times and significantly lower power consumption.

Figure 3: Cross-section of a split-gate flash bit cell. This is Freescale's split-gate TFS (SG-TFS) cell, which places a select gate in series with a nanocrystal-based storage device.

Split-gate technology offers a number of benefits:

???Simple operation: Placing a select gate in series with the charge-storage device allows sector erase without complex algorithms to control leakage.
???Efficient arrays: Most decode circuitry uses compact low-voltage devices for low overhead. Sector overhead is built into array, allowing many small sectors (1 KB for example) without extra area.
???Fast read access: The data path for read operations uses only fast, low-voltage transistors.
???Low-power read/write: Low-voltage data path has a small voltage swing and reduced dynamic power consumption. Programming current required per bit is roughly 10% of that required by conventional 1T flash, which allows it to use smaller, more efficient charge pumps.
Split-gate TFS (SG-TFS) combines all the advantages of split-gate (SG) and nanocrystal-based TFS technologies. It is a type of split-gate cell that combines all of the inherent split-gate advantages with another major innovation: the use of an array of small (less than 100-? diameter) silicon islands to store the data in the cell (figure 4). Because the data storage depends on a large number of these nanocrystals working together to store charge, the SG-TFS cell will retain its overall data state even if one of the individual nanocrystals were to fail. This unique feature provides good retention of the stored data, even if a small defect were to occur during manufacturing.

Figure 4: SG-TFS is a type of split-gate cell that stores data in an array of small (less than 100-? diameter) silicon islands.


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