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TSMC preps CoWoS test car with JEDEC Wide I/O DRAM Interface

Posted: 16 Oct 2012 ?? ?Print Version ?Bookmark and Share

Keywords:CoWoS? Wide I/O? DRAM? JEDEC?

TSMC has revealed that it has taped out what it says is the foundry segment's first Chip on Wafer on Substrate (CoWoS) test vehicle using JEDEC Solid State Technology Association's Wide I/O mobile DRAM interface. According to the company, the milestone demonstrates the industry's system integration trend to achieve increased bandwidth, higher performance and superior energy efficiency.

This generation of TSMC's CoWoS test vehicles added a silicon proof point demonstrating the integration of a logic SoC chip and DRAM into a single module using the Wide I/O interface.

TSMC's CoWoS technology claims to provide the front-end manufacturing through chip on wafer bonding process before forming the final component. Along with Wide I/O mobile DRAM, the integrated chips provide optimised system performance and a smaller form factor with significantly improved die-to-die connectivity bandwidth.

A key to this success is TSMC's close relationship with its ecosystem partners to provide the right features and speed time-to-market. Partners include: Wide I/O DRAM from SK Hynix; Wide I/O mobile DRAM IP from Cadence Design Systems; and EDA tools from Cadence and Mentor Graphics.

CoWoS�is an integrated process technology that attaches device silicon chips to a wafer through chip on wafer (CoW) bonding process. The CoW chip is attached to the substrate (CoW-On-Substrate) to form the final component. TSMC CoWoS�technology has entered the pilot production stage.





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