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TSMC names EDA partners for CoWoS, 20nm

Posted: 17 Oct 2012 ?? ?Print Version ?Bookmark and Share

Keywords:CoWoS? simulation tools? design infrastructure? SoC?

A host of EDA companies have been selected by TSMC as technology partners for its 20nm and CoWoS (Chip on Wafer on Substrate) Reference Flow released last week.

The silicon-validated CoWoS design infrastructure enables multi-die integration to support high bandwidth, low power and can achieve fast time-to-market for 3D IC designs while the 20nm reference flow reduces design complexity and deliver required accuracy through DPT aware capabilities, according to TSMC.

Cadence Design Systems' 3D IC technologies have been validated with development of a CoWoS test vehicle that includes a system on chip with Cadence Wide I/O memory controller and PHY IP as well as the inclusion of its Encounter RTL-to-signoff and Virtuoso custom/analogue platforms. Other products include the Cadence system-in-package and recently acquired Sigrity power-aware chip/package/board signal integrity solution, which helps engineers overcome die-stacking and silicon carriers' challenges.

Mentor Graphics also announced new capabilities to complement TSMC's 20nm manufacturing processes. Enhancements to support both digital and analogue/mixed signal 20nm design infrastructure include new features in the Pyxis IC Station platform, the Eldo fast SPICE simulation products, the Olympus-SoC place and route system, the Calibre nmDRC, Calibre RealTime, Calibre PERC and Calibre xACT 3D solutions, and the Tessent silicon test product suite.

For simulation tools, TSMC turned to ANSYS and subsidiary Apache to meet power, noise and reliability requirements. As part of the 20nm reference flow, Apache made needed enhancements in its RedHawk tool to provide IR-drop and electromigration analysis based on 20nm process requirements such as current direction and power grid rule of DC EM. Meanwhile, Totem, Chip Thermal Model and Sentinel-TI, along with SIwave and Icepak, provide complete system-level thermal analysis with consideration for chip behaviour across CoWoS designs.

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