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ARM's V8 to be used for TSMC's 16nm FinFET

Posted: 18 Oct 2012 ?? ?Print Version ?Bookmark and Share

Keywords:20nm planar? 16nm FinFET? 2.5D stacks?

At the company's recent event, TSMC laid out roadmaps for 20nm planar, 16nm FinFET and 2.5D stacks. The Taiwanese foundry plans to use ARM's first 64bit processor, the V8, as a test vehicle for the 16nm FinFET process with the first tape out of a test chip probably within the next year.

The advent of double patterning at 20 nm and FinFETs at 16 nm pose significant challenges to chip designers, based on talks with TSMC and partner companies. TSMC's roadmap is roughly in line with rival Globalfoundries that also hopes to make 20nm chips next year and 14-nm FinFET chips in 2014.

Based on talks with TSMC and partner companies, the advent of double patterning at 20nm and FinFETs at 16nm pose significant challenges to chip designers. TSMC's roadmap is roughly in line with rival Globalfoundries, which also hopes to make 20nm chips next year and 14nm FinFET chips in 2014.

Figure 1: TSMC aims to start early or "risk" production of 16 nm FinFETS in Nov. 2013.

One analogue IP provider said his first 20 nm designs resulted in bigger blocks, disappointing customers. The company had to completely redesign IP such as USB blocksa job that took a yearto deal with double patterning and get 25 to 30 per cent area reductions.

The USB redesign also was required because the 20-nm process only supports 1.8V transistors. USB requires legacy support for 5V and 3.3V operations.

Top EDA executives said it's too early to tell how similar or different TSMC's 16-nm FinFETs will be compared to those of competitors such as GlobalFoundries. Foundries are just now issuing their first early versions of design rule manuals for their FinFET processes, although some early test structures have been taped out.

Cliff Hou

TSMC's 16-nm FinFET process will be substantially similar to its 20-nm high-K metal gate SoC process in the back-end, said Cliff Hou, vice president of R&D at TSMC, in a conversation with EE Times after his talk here. Other companies are expected to take a similar approach of marrying 14- and 16-nm FinFET structures with their back-end 20- and 22-nm processes.

By grafting 14- and 16-nm FinFET structures on a 20- and 22-nm back-end process, foundries can avoid at least for one node the need for complex and costly triple or quadruple patterning lithography.

Cadence is expected to treat FinFETs as transistors, automating the way they are generated in custom design flows in ways suitable for the target foundry. Despite that offering, some designersespecially those working with analogue and mixed/signal blocks like USB, expect they will have to redesign their cores for FinFETs.

TSMC aims to have chip design kits for its 16-nm process available in January with the first foundation IP blocks such as standard cells and SRAM blocks ready a month later. It will start limited so-called "risk" production of the 16-nm process in November 2013. Production chip tape outs will follow about four or five quarters later.

The FinFET process will have the same leakage power characteristics as the 20-nm process on which it is based. But it will offer a performance boost up to 35 per cent and total power consumption reductions up to 35 per cent compared to 20 nm, said Hou.

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