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TCAD eases FinFET design and variability analysis

Posted: 23 Oct 2012 ?? ?Print Version ?Bookmark and Share

Keywords:MOSFET? Technology CAD? SiGe?

Intel's introduction of FinFET transistors at the 22nm mode culminates many years of research and development of a replacement transistor to the immensely successful planar MOSFET whose progressive miniaturization is largely responsible for the electronics revolution. The need for a successor to the planar MOSFET had long ago been identified. Starting with the 90nm process node, improved transistor performance was achieved with the introduction of stress into the transistor channel in a way that boosts the speed of the electrons and holes traveling within it. However, controlling the transistor leakage in the off-state became progressively more difficult. Keeping the electrons and holes under the electrostatic control of the gate electrode is key to controlling leakage current, but a number of so-called short channel effects undermine the gate control. The introduction of high-k dielectrics as the gate insulator at the 45nm process node effectively extended the life of the planar MOSFET for another two process nodes, but by the 22nm process node the planar MOSFET could hardly offer an attractive balance of performance and leakage.

Intel's FinFETs thus mark the first fundamental change in transistor architecture since the time when the MOSFET replaced the bipolar transistor as the transistor of choice for logic applications. Its performance improvements over the preceding process node are a clear indication of the promise this technology holds. Although the manufacturing of FinFETs is more complex than manufacturing of its planar predecessor, Intel's introduction is a testament to the inevitability of these devices.

While some 22nm processes will continue using planar MOSFETs, the introduction of FinFETs at 22nm has spurred the development of FinFET technology for the 14nm and smaller nodes at other leading integrated device manufacturers and foundries. With change afoot, the design community is rapidly familiarizing itself with these vertical devices and their novel characteristics, many of which revolve around the fin. From the perspective of a designer, the biggest change brought about by the introduction of FinFETs is the relinquishment of the transistor width as a continuous design variable, as the width now becomes quantized, proportional to the number of fins.

The circuit designers can benefit from the understanding of the technological considerations that go into defining the size, shape, doping and stress of the fin. Moreover, the dimensions of today's and future FinFETs are so small that their electrical behavior is heavily susceptible to random process variations. In the remainder of this article we discuss these two points in more detail aided by the insight afforded by Technology CAD (TCAD) simulation, a simulation technology which is instrumental in optimizing the performance and manufacturability of FinFETs.

Figure 1: 3D representation of FinFET structure showing details of the epitaxially grown source/drain regions.

Geometric considerations in FinFETs
FinFETs effectively surround the silicon channel with gates on three sides (left, right and top of the fin). When the fin is thin enough, the short-channel effects responsible for the leakage current become much easier to mitigate under the tighter control of the three-sided gate.

In practice, the design of a FinFET structure is a fairly complicated process as it must contend with such diverse aspects as the integration of high-k metal gates and stress engineering with the incorporation of SiGe and Si:C source/drain regions for PMOS and NMOS, respectively. The structural complexity of FinFETs is clearly seen in figure 1. For the remainder of this section we will focus on the aspects governing the shape of the fin.???

One of the most interesting considerations in designing a FinFET is whether to use sloped fin sidewalls. Stress simulations indicate that sloped sidewalls are mechanically sturdier than vertical ones while impacting electrical performance only minimally. Figure 2 shows a FinFET structure stripped of its source and drain regions and gate electrode. Though the FinFETs shown here are generic, their dimensions and design criteria are representative of current technology. The shallow trench isolation (STI) is filled with silicon dioxide up to a certain level that is below the fin top by the fin height (that is, the geometric parameter H). The high-k gate dielectric contains two monolayers of oxide interlayer sandwiched between the high-k material (HfO2) and the fin.

The Synopsys TCAD simulators Sentaurus Process and Sentaurus Device are used to simulate the fabrication process and transistor electrical performance. The fin channels have moderate doping, somewhat lower than the planar MOSFET. The source and drain are doped with in situ epitaxy doping. The stress engineering, which includes the strained source/drain and stress induced by the strained replacement metal gate, is used to boost the on-state current. Here we contrast the performance difference between rectangular and triangular fin cross sections.

Figure 2: Silicon fin shape options with vertical and sloped sidewalls. Corner rounding radius is 2.5 nm. All three fin shapes have 15 nm wide fin bottom, but different fin top widths. All fin shapes go through the same process flow for a fair comparison.

Figure 3 depicts electron distributions across the fin of NMOS FinFET in the off-state and on-state. In the off-state, the leakage happens in the middle of the fin regardless of the fin shape. This is because the gate controls the currents in the fin periphery that is close to the gate. The middle of the fin is the most remote from the gate and the gate has less leakage control over there. The leakage in the tapered fin is 17% lower than in the rectangular fin with the same fin width at the fin bottom due to the better gate control of the mid-fin.

The on-state current follows the fin perimeter for all FinFET shapes. The 15 nm wide rectangular fin has 24% higher on-current than for the tapered fin. This is due to the combination of several factors, with 14% coming from the larger perimeter length, and the remaining 10% due to no overlapping electron distributions, and no thin-layer induced mobility degradation that hamper the 5 nm wide fin top of the tapered FinFET.

Figure 3: Impact of fin cross section shape on NMOS FinFET performance. The electron density maps are shown across the fin in the middle of the channel length.

The better gate control of the tapered fin improves the drain-induced barrier lowering effect (DIBL) and reduces subthreshold slope (SS) from 85 mV/dec down to a respectable 77 mV/dec.

Similar analysis for the PMOS is shown on figure 4. What is different here is that the off-state leakage happens mainly at the top of the fin rather than at mid-fin. This is caused by the stress engineering being much stronger in the PMOS FinFET than in the NMOS FinFET.

Figure 4: Impact of fin cross section shape on PMOS FinFET performance. The hole density maps are shown across the fin in the middle of the channel length.

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